hi-3200 Holt Integrated Circuits, Inc., hi-3200 Datasheet - Page 13

• Manufacturer Part Number: hi-3200
• Description: Avionics Data Management Engine / Arinc 429 - Can Bus Bridge
• Manufacturer: Holt Integrated Circuits, Inc.

Two registers must be programmed to define the CAN
bus data rate and bit sampling segment times. This
information is transferred directly to the HI-3110 CAN
controller’s BTR0 and BTR1 registers following the rising
edge of the RUN input.
CAN Bus Timing Configuration
CANBTR0 defines the value of the Re-synchronization Jump Width (SJW) and the Baud Rate Prescaler (BRP).
CANBTR1 configures the CAN protocol bit timing segments in terms of time quanta (Tq) and sets the number of
sampling points.
Bit
7:6
5:0
Bit
7
5:0
CANBTR0
(Address 0x8030)
CANBTR1
(Address 0x8031)
Name
SJW1:0
BRP5:0
Name
SAMP
TSEG2-2:0
R/W
R/W
R/W
R/W
R/W
R/W
Default Description
Default Description
0
0
0
0
These bits are used to compensate for phase shifts between different oscillators on the CAN
bus. They define the maximum number of time quanta (Tq) a bit can be shortened or
lengthened to allow the node to achieve re-synchronization to the edge of an incoming signal.
Note that the time quantum (Tq) is the single unit of time within a bit time.
The baud rate prescaler relates the HI-3110 OSCIN clock frequency, fosc, to the CAN bit time
as described in the HI-3110 data sheet.
BRP bits <5:0>
000000: BRP=1
000001: BRP=2
000010: BRP=3
000011: BRP=4
etc.
This bit configures how many samples are taken per bit. 1 = three samples/bit, 0 = one
sample/bit. Bit sampling occurs at the end of Phase Seg 1.
Note: ARINC825 states that there shall be only one sample per bit
Time segment 2 length. Tseg2 = Phase Seg2 of the CAN bit timing specification. Bits
TSEG2-2:0 specify the number of time quanta in Phase Seg2.
Note: Not all combinations are valid, since Phase Seg2 must be greater than SJW.
TSEG2 bits <2:0>
etc.
111111: BRP=64
000: Not valid
001: TSeg2 = 2 Tq clock cycles
010: TSeg2 = 3 Tq clock cycles
111: TSeg2 = 8 Tq clock cycles
HOLT INTEGRATED CIRCUITS
HI-3200, HI-3201
MSB
MSB
7
7
13
6
6
The HI-3110 OSCIN clock frequency must be set to
achieve the desired bit rate. The HI-3200 COSC output
signal provides a convenient 24MHz clock source for the
HI-3110. For a full description of CAN Bus timing
requirements, please refer to the Holt HI-3110 data sheet.
5
5
4
4
3
3
2
2
1
1
LSB
LSB
0
0