hi-3200 Holt Integrated Circuits, Inc., hi-3200 Datasheet - Page 16

• Manufacturer Part Number: hi-3200
• Description: Avionics Data Management Engine / Arinc 429 - Can Bus Bridge
• Manufacturer: Holt Integrated Circuits, Inc.

The HI-3200 supports eight ARINC 429 receive buses
using on-chip receivers to handle the protocol validation.
The eight ARINC 429 RX Control Registers, ARXC0 - 7,
define the characteristics of each receive channel.
The ARINC 429 receive function of the HI-3200 is acti-
vated by setting the A429RX bit in the Master Control
Register.
When an ARINC 429 message is received by the HI-3200
on any bus, it is checked for protocol compliance. Mes-
sages with incorrect encoding are rejected.
The HI-3200 contains an 8K byte memory for storing
ARINC 429 received data. The memory is organized by
channel number and ARINC 429 label value. Four bytes of
memory are dedicated to each channel / label to store the
32-word ARINC 429 message.
ARINC 429 Received Data Management
ARINC 429 Received Data Memory Organization
0x1FFC
0x1FFF
0x000B
0x0008
0x0007
0x0004
0x0003
0x0000
Channel 0, Label 02
Channel 0, Label 01
Channel 0, Label 00
Channel 7, Label FF
Block 2048
Block 1
Block 3
Block 2
HOLT INTEGRATED CIRCUITS
HI-3200, HI-3201
16
A look-up table is used to enable an interrupt on receipt of a
new ARINC 429 message. Look-up table bit positions pre-
loaded with a “1” will cause an Interrupt to be generated.
When a message is received that triggers an Interrupt, that
channel’s Interrupt bit is set in the ARINC 429 Receive
Pending Interrupt Register. If this bit is unmasked in the
ARINC 429 Receive Interrupt Mask Register, the AINT
output pin is asserted. The label number of the ARINC 429
message causing the interrupt is loaded into that chan-
nel’s ARINC 429 Receive Interrupt Address Register
(AIAR0 - AIAR7).
Because the ARINC Receive Memory is organized by
label value, it is not necessary to store the received label
value (first eight bits of the ARINC message) in the
memory. Instead, the first byte is used to store a status
byte.
The six active bits of the status byte are set to “1” when a
new ARINC word is stored in the memory. These bits flag
the ARINC word as new when the location is interrogated
by the host CPU, any of the four ARINC 429 transmit
schedulers or the CAN Bus transmit scheduler.
0x0003
0x0002
0x0001
0x0000
ARINC data byte 4
ARINC data byte 3
ARINC data byte 2
Status Byte
Etc.