lis3dsh STMicroelectronics, lis3dsh Datasheet

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lis3dsh

Manufacturer Part Number
lis3dsh
Description
Mems Digital Output Motion Sensor Ultra Low-power High Performance Three-axis “nano” Accelerometer
Manufacturer
STMicroelectronics
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Features
Applications
Description
The LIS3DSH is an ultra low-power high
performance three-axis linear accelerometer
belonging to the “nano” family with embedded
state machine that can be programmed to
implement autonomous applications.
The LIS3DSH has dynamically selectable full
scales of ±2g/±4g/±6g/±8g/±16g and it is capable
October 2011
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
ultra low-power high performance three-axis “nano” accelerometer
Wide supply voltage, 1.71 V to 3.6 V
Independent IOs supply (1.8 V) and supply
voltage compatible
Ultra low-power consumption
±2g/±4g/±6g/±8g/±16g dynamically selectable
full-scale
I
16-bit data output
Programmable embedded state machines
Embedded temperature sensor
Embedded self-test
Embedded FIFO
10000 g high shock survivability
ECOPACK
Motion controlled user interface
Gaming and virtual reality
Pedometer
Intelligent power saving for handheld devices
Display orientation
Click/double click recognition
Impact recognition and logging
Vibration monitoring and compensation
2
C/SPI digital output interface
®
RoHS and “Green” compliant
Doc ID 022405 Rev 1
MEMS digital output motion sensor
of measuring accelerations with output data rates
from 3.125 Hz to 1.6 kHz.
The self-test capability allows the user to check
the functioning of the sensor in the final
application.
The device can be configured to generate
interrupt signals activated by user defined motion
patterns.
The LIS3DSH has an integrated first in, first out
(FIFO) buffer allowing the user to store data for
host processor intervention reduction.
The LIS3DSH is available in a small thin plastic
land grid array package (LGA) and it is
guaranteed to operate over an extended
temperature range from -40 °C to +85 °C.
Table 1.
LIS3DSHTR
LIS3DSH
codes
Order
Device summary
Temperature
LGA-16 (3x3x1 mm)
range [° C]
-40 to +85
-40 to +85
Package
LGA-16
LGA-16
LIS3DSH
Preliminary data
Packaging
Tape and
www.st.com
Tray
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lis3dsh Summary of contents

Page 1

... The device can be configured to generate interrupt signals activated by user defined motion patterns. The LIS3DSH has an integrated first in, first out (FIFO) buffer allowing the user to store data for host processor intervention reduction. The LIS3DSH is available in a small thin plastic land grid array package (LGA) and it is guaranteed to operate over an extended temperature range from -40 ° ...

Page 2

... Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 2/53 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 022405 Rev 1 LIS3DSH ...

Page 3

... LIS3DSH 6 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1.1 6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.1 6.2.2 6.2.3 7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 INFO1 (0Dh 8.2 INFO2 (0Eh 8.3 WHO_AM_I (0Fh 8.4 CTRL_REG3 (23h 8.5 CTRL_REG4 (20h 8.6 CTRL_REG5 (24h 8.7 CTRL_REG6 (25h 8.8 STATUS (27h 8.9 OUT_T (0Ch 8.10 OFF_X (10h 8.11 OFF_Y (11h 8.12 OFF_Z (12h 8.13 CS_X (13h ...

Page 4

... PR1 (5Ch 8.40 TC1 (5Dh-5E 8.41 OUTS1 (5Fh 8.42 PEAK1 (19h 8.43 CTRL_REG2 (22h 8.44 STx_1 (60h-6Fh 8.45 TIM4_2 (70h 8.46 TIM3_2 (71h 8.47 TIM2_2 (72h - 73h 8.48 TIM1_2 (74h - 75h 8.49 THRS2_2 (76h 8.50 THRS1_2 (77h 8.51 MASK2_B (79h 8.52 MASK2_A (7Ah 8.53 SETT2 (7Bh 8.54 PR2 (7Ch 8.55 TC2 (7Dh-7E 8.56 OUTS2 (7Fh 4/53 Doc ID 022405 Rev 1 LIS3DSH ...

Page 5

... LIS3DSH 8.57 PEAK2 (1Ah 8.58 DES2 (78h Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Doc ID 022405 Rev 1 Contents 5/53 ...

Page 6

... Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. SPI slave timing values Table 6. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 8. LIS3DSH state machines: sequence of state to execute an algorithm . . . . . . . . . . . . . . . . 15 Table 9. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 12. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13 ...

Page 7

... LIS3DSH Table 49. OUT_X_L register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 50. OUT_X_H register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 51. OUT_Y_L register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 52. OUT_Y_H register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 53. OUT_Z_L register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 54. OUT_Z_H register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 55. FIFO control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 56. FIFO mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 57. ...

Page 8

... List of tables Table 101. TC2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 102. OUTS2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 103. OUTS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 104. PEAK2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 105. DES2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 106. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8/53 Doc ID 022405 Rev 1 LIS3DSH ...

Page 9

... Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. LIS3DSH electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Multiple bytes SPI read protocol (2-byte example Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10 ...

Page 10

... TRIMMING REFERENCE CIRCUITS Z INT1/DRDY Doc ID 022405 Rev 1 CS SCL/SPC STATE MACHINES I2C AND CONTROL SDA/SDO/SDI LOGIC SPI SDO/SEL FIFO / INT 1/DRDY TEMP. SENSOR INT 2 CLOCK Pin 1 indicator 13 1 GND Vdd_IO GND NC NC RES SCL/SPC 9 INT2 5 GND (BOTTOM VIEW) LIS3DSH AM10209V1 am10210V1 ...

Page 11

... LIS3DSH Table 2. Pin description Pin Name Vdd_IO Power supply for I/O pins NC Not connected NC Not connected 2 SCL I C serial clock (SCL) SPC SPI serial port clock (SPC) GND 0 V supply 2 SDA I C serial data (SDA) ...

Page 12

... ST2, ST1 bits=01) Doc ID 022405 Rev 1 (a) . (1) Min. Typ. Max. ±2.0 ±4.0 ±6.0 ±8.0 ±16.0 0.06 0.12 0.18 0.24 0.73 0.01 ±40 ±0.5 150 140 590 -40 +85 - OUTPUT[mg] (CNTL5 ST2, ST1 bits=00) LIS3DSH Unit mg/digit mg/digit mg/digit mg/digit mg/digit %/°C mg mg/°C ug/ sqrt(Hz) mg °C ...

Page 13

... LIS3DSH 3.2 Electrical characteristics @ Vdd = 2 °C unless otherwise noted Table 4. Electrical characteristics Symbol Parameter Vdd Supply voltage Vdd_IO I/O pins supply voltage Current consumption in Active IddA mode Current consumption in power- IddPdn down/standby mode VIH Digital high level input voltage VIL Digital low level input voltage ...

Page 14

... When no communication is on-going, data on SDO is driven by internal pull-up resistor. c. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports. 14/53 Parameter ( SPC SO OUT Doc ID 022405 Rev 1 LIS3DSH (1) Value Unit Min. Max. 100 ns 10 MHz ...

Page 15

... LIS3DSH 2 3.3 inter IC control interface Subject to general operating conditions for Vdd and Top. 2 Table slave timing values Symbol Parameter f SCL clock frequency (SCL) t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time ...

Page 16

... Supply voltage on any pin should never exceed 4.8 V This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. This is an ESD sensitive device, improper handling can cause permanent damage to the part. 16/53 Ratings Doc ID 022405 Rev 1 LIS3DSH Maximum value Unit -0.3 to 4.8 V -0.3 to 4.8 V -0.3 to Vdd_IO +0.3 V 3000 for 0 ...

Page 17

... LIS3DSH 3.5 Terminology 3.5.1 Sensitivity Sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing so, ± ...

Page 18

... The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller. The LIS3DSH features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device. ...

Page 19

... LIS3DSH 4 Application hints Figure 5. LIS3DSH electrical connection Vdd Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO The device core is supplied through the Vdd line while the I/O pins are supplied through the Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF) should be placed as near as possible to pin 14 of the device (common design practice) ...

Page 20

... Digital main blocks 5.1 State machine The LIS3DSH embeds two state machines able to run a user defined program. The program is made set of instructions that define the transition to successive states. Conditional branches are possible. From each state ( possible to have transition to the next state (n+ reset state. ...

Page 21

... FIFO LIS3DSH embeds an acceleration data FIFO for each of the three output channels and Z. This allows a consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO ...

Page 22

... Digital interfaces 6 Digital interfaces The registers embedded inside the LIS3DSH may be accessed through both the I SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I CS line must be tied high (i.e. connected to Vdd_IO). ...

Page 23

... If they match, the device considers itself addressed by the master. The slave address (SAD) associated to the LIS3DSH is 00111xxb whereas the xx bits are modified by the SEL/SDO pin in order to modify the device address. If the SEL pin is connected to the voltage supply, the address is 0011101b, otherwise the address is 0011110b if the SEL pin is connected to ground ...

Page 24

... In the presented communication format, MAK is Master acknowledge and NMAK is No Master Acknowledge. 6.2 SPI bus interface The LIS3DSH SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. 24/53 ...

Page 25

... LIS3DSH Figure 6. Read and write protocol CS SPC SDI SDO CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output ...

Page 26

... AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 022405 Rev 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 LIS3DSH AM10130V1 AM10131V1 ...

Page 27

... LIS3DSH 6.2.2 SPI write Figure 9. SPI write protocol CS SPC SDI RW The SPI Write command is performed with 16 clock pulses. Multiple byte write command is performed adding blocks of 8 clock pulses at the previous one. bit 0: WRITE bit. The value is 0. bit 1 -7: address AD(6:0). This is the address field of the indexed register. ...

Page 28

... AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Multiple read command is also available in 3-wire mode. 28/53 MS AD5 AD2 AD1 AD 0 Doc ID 022405 Rev DO4 DO3 DO2 DO1 DO0 LIS3DSH AM10134V1 ...

Page 29

... LIS3DSH 7 Register mapping Table 16 provides a list of the 8/16-bit registers embedded in the device and the related address: Table 16. Register address map Name INFO1 INFO2 WHO_AM_I CTRL_REG3 CTRL_REG4 CTRL_REG5 CTRL_REG6 STATUS OUT_T OFF_X OFF_Y OFF_Z CS_X CS_Y CS_Z LC_L LC_H STAT VFC_1 VFC_2 ...

Page 30

... Doc ID 022405 Rev 1 LIS3DSH Default Comment 0000 0000 FIFO registers - 0000 0000 SM1 control register SM1 code register - (X =1-16 SM1 general timer - - - SM1 threshold value 1 - SM1 threshold value 2 - SM1 axis and sign mask ...

Page 31

... LIS3DSH Table 16. Register address map (continued) Name PR2 TC2 OUTS2 PEAK2 DES2 Register address Type Hex Binary r 7C 01111100 01111101 r 7D-7E 01111110 r 7F 01111111 r 1A 00011010 w 78 01111000 Doc ID 022405 Rev 1 Register mapping Default Comment - Program-reset pointer - Timer counter Main set flag ...

Page 32

... Interrupt 2 enable/disable. Default value:0 INT2_EN 0 = INT2 signal disabled INT2 signal enabled Interrupt 2 enable/disable. Default Value:0 INT1_EN 0 = INT1/DRDY signal disabled INT1/DRDY signal enabled 32/ IEL INT2_EN INT1_EN Doc ID 022405 Rev 1 LIS3DSH VFILT - STRT ...

Page 33

... LIS3DSH Table 21. CTRL_REG3 register description (continued) Vector filter enable/disable. Default value:0 VFILT 0 = vector filter disabled vector filter enabled Soft reset bit STRT soft reset soft reset (POR function) 8.5 CTRL_REG4 (20h) Control register 4. Table 22. Control register 4 ODR3 ODR2 Table 23. CTRL_REG4 register description ...

Page 34

... Control register 6. Table 28. Control register 6 BOOOT FIFO_EN 34/53 FSCALE2 FSCALE1 FSCALE0 ST1 0 Normal mode 1 Positive sign self-test 0 Negative sign self-test 1 Not allowed ADD_ P1_ WTM_EN INC EMPTY Doc ID 022405 Rev 1 LIS3DSH ST2 ST1 SIM Self test mode P2_ P1_OVER P1_WTM RUN BOOT ...

Page 35

... LIS3DSH Table 29. Control register 6 description BOOT Force reboot, cleared as soon as the reboot is finished. Active high. FIFO_EN FIFO enable. Default value 0. 0=disable; 1=enable WTM_EN Enable FIFO Watermark level use. Default value 0. 0=disable; 1=enable ADD_INC Register address automatically incremented during a multiple byte access with a serial interface (I 0=disable ...

Page 36

... Offset correction Y-axis register, signed value. Table 35. Offset Y default value 0 0 8.12 OFF_Z (12h) Offset correction Z-axis register, signed value. Table 36. Offset Z default value 0 0 36/53 Temp5 Temp4 Temp3 Temperature data Doc ID 022405 Rev 1 LIS3DSH Temp2 Temp1 Temp0 ...

Page 37

... LIS3DSH 8.13 CS_X (13h) Constant shift signed value X-axis register - state machine only. Table 37. Constant shift X-axis default value 0 0 8.14 CS_Y (14h) Constant shift signed value Y-axis register - state machine only. Table 38. Constant shift Y-axis default value 0 0 8.15 CS_Z (15h) Constant shift signed value Y-axis register - state machine only. ...

Page 38

... Vector coefficient register 3 for FSM2 filter. Table 46. Vector filter coefficient register 3 default value 0 0 8.21 VFC_4 (1Eh) Vector coefficient register 4 for DIff filter. Table 47. Vector filter coefficient register 4 default value 0 0 38/ Doc ID 022405 Rev 1 LIS3DSH ...

Page 39

... LIS3DSH 8.22 THRS3 (1Fh) Threshold value e register. Table 48. Threshold value register 3 default value 0 0 8.23 OUT_X (28h - 29h) X-axis output register. Table 49. OUT_X_L register default value 0 0 Table 50. OUT_X_H register default value 0 0 8.24 OUT_Y (2Ah - 2Bh) Y-axis output register. Table 51. OUT_Y_L register default value ...

Page 40

... EMPTY FSS4 FSS3 Doc ID 022405 Rev 1 LIS3DSH WTMP2 WTMP1 WTMP4 Mode Bypass Mode. FIFO turned off FIFO Mode. Stop collecting data when FIFO is full. Stream Mode. If the FIFO is full the new sample overwrites the older one Stream mode until trigger is de- ...

Page 41

... LIS3DSH Table 58. FIFO_SRC register description WTM OVRN_FIFO EMPTY FSS4-FSS0 8.28 CTRL_REG1 (21h) SM1 control register. Table 59. SM1 control register HYST2_1 HYST1_1 Table 60. SM1 control register structure HYST2_1 Hysteresis unsigned value to be added or subtracted from threshold value in SM1 HYST1_1 Default value=000 HYST0_1 0=SM1 interrupt routed to INT1, 1=SM1 interrupt routed to INT2 pin ...

Page 42

... Table 67. THRS2_1 default value 0 0 8.35 THRS1_1 (57h) Threshold value for SM1 operation. Table 68. THRS1_1 default value 0 0 42/ Doc ID 022405 Rev 1 LIS3DSH ...

Page 43

... LIS3DSH 8.36 MASK1_B (59h) Axis and sign mask (swap) for SM1 motion detection operation. Table 69. MASK1_B axis and sign mask register P_X N_X Table 70. MASK1_B register structure P_X 0=X + disabled, 1=X + enabled N_X 0=X - disabled, 1=X – enabled P_Y 0=Y+ disabled, 1=Y + enabled N_Y 0=Y- disabled, 1=Y – enabled P_Z ...

Page 44

... TC1 (5Dh-5E) 16-bit general timer (unsigned output value) for SM1 operation timing. Table 77. TC1_L default value 0 0 Table 78. TC1_H default value 0 0 44/53 ABS - - PP1 PP0 RP3 Doc ID 022405 Rev 1 LIS3DSH THR3_MA R_TAM SITR RP2 RP1 RP0 ...

Page 45

... LIS3DSH 8.41 OUTS1 (5Fh) Output flags on axis for interrupt SM1 management. Table 79. OUTS1 register P_X N_X Read action of this register, depending on the flag affects SM1 interrupt functions. Table 80. OUTS1 register description P_X 0 show, 1=X+ show N_X 0 show, 1=X – show P_Y 0 show, 1=Y + show N_Y 0 show, 1=Y – ...

Page 46

... Timer3 default value 0 0 8.47 TIM2_2 (72h - 73h) 16-bit general timer (unsigned value) for SM2 operation timing. Table 86. TIM2_2_L default value 0 0 Table 87. TIM2_2_H default value 0 0 46/ Doc ID 022405 Rev 1 LIS3DSH ...

Page 47

... LIS3DSH 8.48 TIM1_2 (74h - 75h) 16-bit general timer (unsigned value) for SM2 operation timing. Table 88. TIM1_2_L default value 0 0 Table 89. TIM1_2_H default value 0 0 8.49 THRS2_2 (76h) Threshold signed value for SM2 operation. Table 90. THRS2_2 default value 0 0 8.50 THRS1_2 (77h) Threshold signed value for SM2 operation. ...

Page 48

... Default value: 0 ABS 0=unsigned thresholds, 1=signed thresholds Default value: 0 THR3_MA 0=no action, 1=threshold 3 limit value for axis and sign mask reset (MASK2_A) 48/53 P_Y N_Y P_Z ABS - - Doc ID 022405 Rev 1 LIS3DSH N_Z P_V N_V THR3_MA R_TAM SITR ...

Page 49

... LIS3DSH Table 97. SETT2 register description Next condition validation flag. Default value:0 R_TAM 0=no valid next condition found, 1=valid next condition found and reset Default value: 0 SITR 0=no actions, 1=program flow can be modified by STOP and CONT commands 8.54 PR2 (7Ch) Program and reset pointer for SM2 motion detection operation. ...

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... Registers marked as ‘Reserved’ must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 50/ Doc ID 022405 Rev 1 LIS3DSH ...

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... LIS3DSH 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK trademark. Figure 12. LGA-16: mechanical data and package dimensions R ef ...

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... Revision history 10 Revision history Table 106. Document revision history Date 26-Oct-2011 52/53 Revision 1 Initial release. Doc ID 022405 Rev 1 LIS3DSH Changes ...

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... LIS3DSH Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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