k9f5608u0c Samsung Semiconductor, Inc., k9f5608u0c Datasheet - Page 10

• Manufacturer Part Number: k9f5608u0c
• Description: 32m X 8 Bit 16m X 16 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PRODUCT INTRODUCTION
The K9F56XXX0C is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device)
columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device).
device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buff-
ers and memory during page read and page program operations.The memory array is made up of 16 cells that are serially connected
to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND
structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array
consists of 2048 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase oper-
ation is prohibited on the K9F56XXX0C.
The K9F56XXX0C has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). K9F5616X0C allows sixteen bit wide data
transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows
systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written
through I/O s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one
bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other com-
mands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for
execution. The 32M-byte(X8 device) or 16M-word(X16 device) physical space requires 24 addresses(X8 device) or 23
addresses(X16 device), thereby requiring three cycles for word-level addressing: column address, low row address and high row
address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In
Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific com-
mands into the command register. Table 1 defines the specific commands of the K9F56XXX0C.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
NOTE : 1. The 01h command is available only on X8 device(K9F5608X0C).
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
K9F5608Q0C
K9F5608D0C
K9F5608U0C
Read 1
Read 2
Read ID
Reset
Page Program
Copy-Back Program
Lock
Unlock
Lock-tight
Read Block Lock Status
Block Erase
Read Status
Function
K9F5616Q0C
K9F5616U0C
K9F5616D0C
1st. Cycle
00h/01h
FFh
2Ah
2Ch
7Ah
50h
90h
80h
00h
23h
60h
70h
(1)
10
2nd. Cycle
D0h
10h
8Ah
24h
-
-
-
-
-
-
-
-
Acceptable Command during Busy
FLASH MEMORY
O
O
A 528-byte(X8