k9f5608u0c Samsung Semiconductor, Inc., k9f5608u0c Datasheet - Page 31

• Manufacturer Part Number: k9f5608u0c
• Description: 32m X 8 Bit 16m X 16 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 528
ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array.
The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which
up to 528 bytes
ming period where the loaded data is programmed into the appropriate cell. About the pointer operation, please refer to the attached
technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by mon-
itoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid
while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read
Status command mode until another valid command is written to the command register.
Figure 10. Program Operation
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution
of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with
"00h" command with the address of the source page moves the whole 528bytes/264words(X8 device:528bytes, X16
device:264words) data into the internal buffer. As soon as the Flash returns to Ready state, copy-back programming command "8Ah"
may be given with three address cycles of target page followed. The data stored in the internal buffer is then programmed directly into
the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into the
copied pages is prohibited before erase. Since the memory array is internally partitioned into two different planes, copy-back program
is allowed only within the same memory plane. Thus, A14, the plane address, of source and destination page address must be the
same.
Figure 11. Copy-Back Program Operation
K9F5608Q0C
K9F5608D0C
K9F5608U0C
R/B
R/B
I/Ox
I/Ox
00h
(X8 device)
80h
(X8 device) or
Source Address
Add.(3Cycles)
K9F5616Q0C
K9F5616U0C
K9F5616D0C
or 264 words
Address & Data Input
264
(X16 device)
(X16 device)
t
R
, in a single page program cycle. The number of consecutive partial page program-
of data may be loaded into the page register, followed by a non-volatile program-
10h
8Ah
Destination Address
Add.(3Cycles)
31
t
PROG
t
PROG
70h
70h
FLASH MEMORY
I/O
Fail
I/O
Fail
0
0
Pass
Pass