k9f5608u0c Samsung Semiconductor, Inc., k9f5608u0c Datasheet - Page 7

• Manufacturer Part Number: k9f5608u0c
• Description: 32m X 8 Bit 16m X 16 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PIN DESCRIPTION
NOTE : Connect all V
K9F5608Q0C
K9F5608D0C
K9F5608U0C
(K9F5608X0C)
(K9F5616X0C)
I/O
Pin NAME
I/O
LOCKPRE
Do not leave V
0
Vcc
DNU
0
CLE
ALE
R/B
Vcc
Vss
N.C
WE
WP
CE
RE
~ I/O
~ I/O
Q
15
7
CC
CC
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage
generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the
all blocks go to lock state.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
OUTPUT BUFFER POWER
Vcc
Vcc
POWER
V
GROUND
NO CONNECTION
Lead is not internally connected.
DO NOT USE
Leave it disconnected
LOCK MECHANISM & POWER-ON AUTO-READ ENABLE
To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high,
Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block
Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on
3.3V device(K9F56XXU0C).
Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C
and V
CC
or V
K9F5616Q0C
K9F5616U0C
K9F5616D0C
Q
Q
is the power supply for device.
is the power supply for Output Buffer.
is internally connected to Vcc, thus should be biased to Vcc.
SS
SS
disconnected.
pins of each device to common power supply outputs.
7
Pin Function
FLASH MEMORY