cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 127

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
5.7.14
Table 5-38. RSIU Group State Register
5.7.15
Table 5-39. RSIU Port Configuration Register (1 of 2)
28560-DSH-001-B
Field
31:15
31:2
Bit
1:0
Bit
14
13
12
RSVD
GROUP_STATE
RSVD
RGSYNC_EDGE
RXENBL
RSVD
Field Name
Name
RSIU Group State Register
RSIU Port Configuration Register
This memory is used internally by the RSIU. The state field of groups belonging to
one port must be set to zero (i.e., disable state) before the port is enabled. The relevant
group register is found at an offset of the group number from the base address. There
is one register per group.
There is a Receive Port Configuration register for each serial port. It defines how the
CX28560 interprets and synchronizes the received bit streams associated with the
serial port.
Table 5-39
Value
Value
0
0
1
2
3
0
0
1
0
1
0
Reserved
Disable state, where Group is disabled
Enable state, where Group is enabled
Polling state – polling handling
RSVD
Reserved.
Receiver GSYNC—Falling Edge
Receiver GSYNC—Rising Edge
Receive Port Disabled. Logically resets the time slot, regardless of RTS_ENABLE bit
field in RSIU Time Slot Configuration Descriptor. This does not affect the bit values in
any time slot descriptor.
Receive Port Enabled. This bit field acts as a logical AND between RTS_ENABLE bit field
in RSIU Time Slot Configuration Descriptor and time slot.
Logically, if RTS_ENABLE bit field in RSIU Time Slot Configuration Descriptor is
enabled, it allows all channels with time slot enable bits set to start processing data.
This does not affect the bit values in any time slot descriptor.
Reserved.
describes the bit fields in RSIU Port Configuration register.
Mindspeed Technologies™
Advance Information
Description
Description
The CX28560 Memory Organization
5
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