cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 190

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

Electrical and Mechanical Specification
Figure 8-10. EBUS Write/Read Cycle, Motorola-Style
8-14
NOTE(S):
1. BG* assertion depends on the external bus arbiter. While BG* and BR* are both deasserted, CX28560 places shared EBUS
2. One ECLK cycle after BG* assertion, CX28560 outputs valid command bus signals: EBE, AS*, R/WR*, and DS*.
3. Two ECLK cycles after BG* assertion, CX28560 outputs valid EAD address signals. BGACK* assertion occurs three ECLK
4. ALAPSE inserts a variable number of ECLK cycles to extend AS* high pulse width and EAD address interval.
5. EAD address remains valid for one ECLK cycle after AS* falling edge. During a write transaction, CX28560 asserts R/WR*
6. ELAPSE inserts a variable number of ECLK cycles to extend DS* low pulse width and EAD data interval. Read data inputs
7. EAD write data, EBE, R/WR* and AS* signals remain valid for one ECLK cycle after BGACK* and DS* are deasserted.
8. One ECLK cycle after BGACK* deassertion, the BR* output is deasserted and the bus is parked (command bus deasserted,
9. Command bus is unparked (three-stated) one ECLK after BG* deassertion; two different unpark phases are shown,
10. BLAPSE inserts a variable number of ECLK cycles to extend BR* deassertion interval until the next bus request.
signals in high impedance (three-state, shown as dashed lines).
cycles after BG* and BR* are both asserted.
and outputs valid EAD write data one ECLK prior to DS* assertion. During a read transaction, EAD data lines are inputs.
are sampled on ECLK rising edge coincident with DS* deassertion.
EAD three-state). The bus parked state ends when the external bus arbiter deasserts BG*.
indicating the dependence on BG* deassertion. If BG* remained asserted until the next bus request, then command bus
remains parked until one ECLK following the next BR* assertion. Caution: Whenever BG* is deasserted, all shared EBUS
signals are forced to three-state after one ECLK cycle, regardless of whether the EBUS transaction was completed.
CX28560 does not reissue or repeat such an aborted transaction.
R/WR*(write)
R/WR*(read)
EAD[31:0]
See Notes
EBE[3:0]*
BGACK*
ECLK
BG*
BR*
DS*
AS*
1
2
Mindspeed Technologies™
Byte Enables from PCI Data Phase
3
ALAPSE - 0
Address
Advance Information
5
ELAPSE - 0
Data
6
7
8
9
BLAPSE - 0
10
CX28560 Data Sheet
28560-DSH-001-B