cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 82

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Serial Interface
4.6.1
4.6.2
4-8
Frame Synchronization Flywheel
Change Of Frame Alignment (COFA)
To maintain a time-base, in Conventional mode, the CX28560 uses the TSYNC
and RSYNC signals. These signals keep track of the active bit in the current time
slot. The mechanism is referred to as the frame synchronization flywheel. The
flywheel counts the number of bits per frame and automatically rolls over the bit
count according to the programmed mode. The TSYNC or RSYNC input marks
the first bit in the frame. The mode specified in the RPORT_TYPE bit field and
TPORT_TYPE bit and the start and end address of time slot pointer determine the
number of bits in the frame. A flywheel exists for both the transmit and the
receive functions for every port.
The flywheel is synchronized when the CX28560 detects TSYNC = 1 or RSYNC
= 1, for transmit or receive functions, respectively. Once synchronized, the
flywheel maintains synchronization without further assertion of the
synchronization signal.
A time slot counter within each port is reset at the beginning of each frame and
tracks the current time slot being serviced.
NOTE:
A Change Of Frame Alignment (COFA) condition is defined as a frame
synchronization event detected when it was not expected, and also includes the
detection of the first occurrence of frame synchronization in the receive direction.
In unchannelized mode, there are no COFA conditions because the TSYNC and
RSYNC signals are ignored in this mode.
When the serial interface detects a COFA condition, an internal COFA signal is
asserted until the COFA condition is declared off. A COFA condition is declared
off when there was a complete frame without an unexpected SYNC pulse. Thus,
an internal COFA signal is asserted for at least two frame periods. During the
frame period that the internal COFA is asserted, the CX28560’s serial line
processor (SLP) terminates all messages found to be active during the COFA
condition relevant to that port.
Assertion of COFA condition generates a COFA interrupt encoded in the
Interrupt Status Descriptor (ISD) toward the host if this interrupt is unmasked
(see RCOFA_EN or/and TCOFA_EN bit fields). If a synchronization signal
(SYNC) is received (low to high transition on TSYNC or RSYNC) while the
internal COFA is asserted, an interrupt descriptor with the COFA interrupt
encoding is generated immediately if this interrupt is not masked. When the
internal COFA is deasserted, the CX28560 generates an interrupt descriptor with
CREC event encoding if the interrupt is unmasked—this includes the COFA
caused by the first sync received in the receive direction.
On assertion of the internal COFA, in the receive direction an end of message
status is prepared with the error encoding set to COFA and passed to the system.
The receive serial bit stream processing resumes when the COFA condition is
declared off. If channels are configured in HDLC mode, channels resume
immediately after the COFA condition is declared off. When configured to
transparent mode, channels start operating in the first time slot assigned to the
logical channel. Thus, after an RxCOFA, no channel recovery action is required
because the channel recovers automatically.
In unchannelized mode, the CX28560 ignores the synchronizing signals
and the frame synchronization flywheel mechanism is ignored.
Mindspeed Technologies™
Advance Information
CX28560 Data Sheet
28560-DSH-001-B