cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 241

• Manufacturer Part Number: cx28560
• Description: Hdlc Controller
• Manufacturer: Mindspeed Technologies

CX28560 Data Sheet
D.2
D.2.1
28560-DSH-001-B
Timing Details
Payload Bus, AC Characteristics
The TSBUS device operates as the master of the transmit TSBUS and the
CX28560 (HDLC Controller) device responds as slave. TSBUS generates
TSBUS clocks and control signals and the CX28560 device responds by
transmitting TSBUS data to or receiving TSBUS data from TSBUS.
TSBUS generates a TSBUS Frame Strobe (TSB_STB) on the rising edge of
TSB_CLK as seen in
indicates the start of an N time slot Frame carrying payload data.
The Time Slot bus exchanges data over two I/O chip boundaries so care must be
taken in ensuring that the data is exchanged on the right phase of the master
TSBUS clock TSB_CLK. A possible solution for ensuring correct data exchange
is for the Slave (CX28560) to transmit data on the Rising edge of TSB_CLK, and
sample the Received data on the falling edge of TSB_CLK.
There is only one Time Slot Frame strobe used (TSB_STB) for transmit and
receive direction. There is also only one clock (TSB_CLK) used in the definition
of bit boundaries for transmit and receive. This results in the Time Slot Frame
alignment of the receive and transmit payload (illustrated in
time slot in the Time Slot Bus consists of eight serial data bits. The MSB bit for
each time slot is transmitted first.
Mindspeed Technologies™
Advance Information
Figure
D-2. The Time Slot Bus frame strobe TSB_STB
Figure
D-2). Each
TSBUS
D
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7