cx28560 Mindspeed Technologies, cx28560 Datasheet - Page 267
cx28560
Manufacturer Part Number
cx28560
Description
Hdlc Controller
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28560.pdf
(274 pages)
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Figure G-1. PCI Burst Write: Two 32-bit Fast Back-to-Back Transactions to Same Target
28560-DSH-001-B
C/BE#[3:0]
DEVSEL#
FRAME#
AD[31:0]
TRDY#
IRDY#
PAR
CLK
Appendix G: Example of an
Figure G-1
operating as a master, and fast back-to-back feature enabled. CX28560 performs as a
master while operating at 32-bit address-data, a burst write of 2 dwords, which are
transferred during the first cycle and a burst write of 3 dwords, which are transferred
during the second cycle. Both transaction cycles require 4 PCLK cycles.
Bus Cmd
Address
illustrates, in a specific configuration, CX28560’s PCI transactions while
Mindspeed Technologies™
Data1
BE1
Advance Information
Data2
BE2
Arbitration for Fast and
Non-Fast Back-to-Back
Transactions
Bus Cmd
Address
Data1
BE1
Data2
BE2
Data3
BE3
G
-
1
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