lc89058w Sanyo Semiconductor Corporation, lc89058w Datasheet - Page 20

• Manufacturer Part Number: lc89058w
• Description: Cmos Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

10.1.3 Switching between master clock and clock source
• The RMCK, RBCK, and RLRCK (hereunder, R system), and the SBCK and SLRCK (hereunder, S system) clock
• Clock source switching is to set with the R and S systems interlocked. This setting is carried out with OCKSEL.
• The clock source is automatically switched to the PLL or XIN clock by locking/unlocking the PLL. The clock source
• The PLL status can be always monitored with RERR even after switching to the XIN source. Moreover, the processed
10.1.4 Points to notice about switching clock source while PLL is locked
• It is necessary to set the oscillation amplifier to the continuous operation mode at the same time with AMPOPR [1:0]
• In the state where the PLL is locked, if the clock is switched to XIN source with OCKSEL while the oscillator
information can be read with the microcontroller interface regardless of the PLL status.
to do the clock switch to the XIN source with OCKSEL when the oscillation amplifier has stopped in the state where
the PLL is locked. The clock is not output when switching to the XIN clock source without executing this setting.
amplifier is stopped, RERR is temporarily outputs an error (high level) indication. When switched to XIN source, the
oscillator amplifier is switched to the operating state at the same time.
RERR is temporality outputs an error (H level) indication when the oscillation amplifier switches from the stop
condition to the continuous mode. Consequently the input fs calculation restarts. At this time, the previous fs
calculation value is reset and compared with the newly calculated fs value. Then those two values are found not
identical, that’s why the error is temporarily issued.
can be switched to XIN with OCKSEL, regardless of the PLL status.
Table 10.1: Relationship between Clock Source Switch Commands and Clock Sources when PLL Locked/Unlocked
sources can be selected between the following two master clocks.
(1) PLL source (512fs)
(2) XIN source (12.288MHz or 24.576MHz)
OCKSEL
0
1
Locked
R System Clock Source
PLL
XIN
LC89058W-E
Unlocked
XIN
XIN
Locked
S System Clock Source
PLL
XIN
Unlocked
XIN
XIN
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