lc89058w Sanyo Semiconductor Corporation, lc89058w Datasheet - Page 25

• Manufacturer Part Number: lc89058w
• Description: Cmos Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

10.1.9 Output of clock switch transition signal (CKST)
• CKST outputs pulse when the output clock changes by PLL lock/unlock.
• The polarity of the CKST pulse output can be reversed with CKSTP. Subsequently, CKSTP is assumed to be 0.
• In the lock-in stage, the CKST falls at the word clock generated from the XIN clock after PLL is locked following
• In the unlock stage, the CKST falls at the same timing as RERR, PLL lock detection signal, and rises after word
• Change of the PLL lock status and timing of the clock change can be seen by detecting the rising and falling edges
• The clock is switched after the PLL lock condition is tested and identified. The timing of this clock switching is
• A free-running clock is output from the clock output pin immediately after PLL unlocking.
detection of input data, and rises at the same timing as RERR after a designated period.
clocks generated from the XIN clock are counted for a designated period.
and pulses of CKST.
determined by setting the PTOXW [1:0]. The initial value is such that the clock is switched in 2.7ms after the falling
edge of CKST. The value, however, assumes that the oscillation amplifier is set to permanent operation mode. If the
oscillation amplifier is set to be stopped after PLL locking, the startup time before the oscillation amplifier stabilizes
after PLL unlocking, is added.
RX0 to RX6
RX0 to RX6
PLL status
PLL status
PLL clock
PLL clock
XIN clock
XIN clock
RMCK
RMCK
RERR
RERR
CKST
CKST
(CKSTP=0)
(CKSTP=0)
**: When set to PTOXW[1:0]=00 (max.)
Digital data
UNLOCK
LOCK
XIN clock
Figure 10.5 Clock Switch Timing
PLL clock
LC89058W-E
Digital data
(a): Lock-in stage
Same timing as RERR
(b): Unlock stage
After PLL lock
3ms to 144ms
2.7ms
UNLOCK
LOCK
PLL clock
2.7ms**
5.3ms
XIN clock
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