lc89058w Sanyo Semiconductor Corporation, lc89058w Datasheet - Page 26

• Manufacturer Part Number: lc89058w
• Description: Cmos Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

10.1.10 Output clocks generated when input S/PDIF reception is limited
• The same processing performed when the PLL is unlocked is carried out if an S/PDIF input exceeding the reception
range limit (which can be defined by FSLIM[1:0]) is supplied. The clock source is then switched to the XIN clock and
clocks are output from respective clock pins.
PLL status
PLL status
PLL status
RLRCK
RLRCK
RLRCK
DIN0-6
DIN0-6
DIN0-6
RMCK
RMCK
RMCK
RERR
RBCK
RERR
RBCK
RERR
RBCK
Figure 10.6 Output Clocks Generated When Input Data Reception Is Limited
fs=44.1kHz
fs=44.1kHz
fs=44.1kHz
PLL clock
PLL clock
PLL clock
(b) When set to FSLIM[1:0]=01 (Receive frequency is limited to 96kHz or lower)
(c) When set to FSLIM[1:0]=10 (Receive frequency is limited to 48kHz or lower)
LOCK
LOCK
LOCK
(a) When set to FSLIM[1:0]=00 (No limit on inputs)
LC89058W-E
fs=192kHz
fs=192kHz
fs=192kHz
XIN clock
PLL clock
LOCK
LOCK
LOCK
XIN clock
XIN clock
PLL clock
fs=96kHz
fs=96kHz
fs=96kHz
UNLOCK
PLL clock
LOCK
LOCK
LOCK
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