lc89058w Sanyo Semiconductor Corporation, lc89058w Datasheet - Page 24

• Manufacturer Part Number: lc89058w
• Description: Cmos Digital Audio Interface Receiver
• Manufacturer: Sanyo Semiconductor Corporation

10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK)
• The relationships between the output clock and switch function are shown below.
• PLL in the figure indicates the PLL source and XIN the XIN source.
• The contents in the quotation marks “∗∗∗” by the switch function blocks correspond to the write command names.
• The broken lines connecting the switches indicate coordinated switching.
• Lock/Unlock is switched automatically by PLL locking/unlocking.
Master
Clock
Generator
PLL Source
512fs
X’tal Source
12.288MHz
24.576MHz
512fs
12.288MHz
24.576MHz
“PLLDV0”
“PLLDV1”
128fs
Mute
512fs
256fs
128fs
64fs
32fs
16fs
fs/2
fs/4
1/1
1/2
1/4
2fs
fs
“PSBCK[1:0]”
“PSLRCK[1:0]”
“XINSEL”
“PRSEL[1:0]”
Figure 10.4 Clock Output Block Diagram
Input fs
Auto
12.288MH
6.144MHz
3.072MHz
12.288MH
6.144MHz
3.072MHz
LC89058W-E
192kHz
192kHz
96kHz
48kHz
96kHz
48kHz
Mute
Mute
Mute
Mute
Mute
64fs
Mute
1/1
1/2
1/4
1/1
1/2
fs
“XMSEL[1:0]”
“XRBCK[1:0]”
“XSBCK[1:0]”
“XRSEL[1:0]”
“XRLRCK[1:0]”
“XSLRCK[1:0]”
“SLRCKP”
“SBCKP”
“PLLACC”
XIN
PLL
PLL
XIN
PLL
XIN
PLL
XIN
PLL
XIN
Lock / Unlock
GPIO0
GPIO1
GPIO2
“OCKSEL”
“RMCKP”
“EMCKP”
Master / Slave
“EXTSEL”
RLRCK
SLRCK
RMCK
XMCK
RBCK
SBCK
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