ADF4116 Analog Devices, ADF4116 Datasheet - Page 10

• Manufacturer Part Number: ADF4116
• Description: Single, Integer-n 550 MHZ PLL
• Manufacturer: Analog Devices

ADF4116/ADF4117/ADF4118
PRESCALER (P/P + 1)
The dual modulus prescale (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized, (N =
PB + A). The dual-modulus prescaler takes the CML clock from
the RF input stage and divides it down to a manageable frequency
for the CMOS A and B counters. The prescaler is program-
mable. It can be set in software to 8/9 for the ADF4116, and
set to 32/33 for the ADF4117 and ADF4118. It is based on a
synchronous 4/5 core.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
f
P
B
A
f
R
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no dead zone in the PFD transfer function and
gives a consistent reference spur level.
VCO
REFIN
INPUT STAGE
Output Frequency of external voltage controlled oscilla-
tor (VCO).
Preset modulus of dual modulus prescaler.
Preset Divide Ratio of binary 13-bit counter (3 to 8191).
Preset Divide Ratio of binary 5-bit swallow counter
(0 to 31).
Output frequency of the external reference frequency
oscillator.
Preset divide ratio of binary 14-bit programmable refer-
ence counter (1 to 16383).
FROM RF
MODULUS
CONTROL
f
VCO
N = BP + A
PRESCALER
= [(P × B) + A] × f
P/P + 1
LOAD
LOAD
COUNTER
COUNTER
13-BIT B
5-BIT A
REFIN
/R
TO PFD
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4116 family allows the
user to access various internal points on the chip. The state
of MUXOUT is controlled by M3, M2, and M1 in the func-
tion latch. Table V shows the full truth table. Figure 6 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect.
Digital Lock Detect is active high. It is set high when the phase
error on three consecutive phase detector cycles is less than 15 ns.
It will stay set high until a phase error of greater than 25 ns is
detected on any subsequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected it is high with narrow low-going pulses.
CP OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R DIVIDER
N DIVIDER
R COUNTER OUTPUT
N COUNTER OUTPUT
R DIVIDER
N DIVIDER
HI
HI
SDOUT
D1
D2
CLR1
CLR2
U1
U2
Q1
Q2
MUX
UP
DOWN
DELAY
U3
CONTROL
CP GND
DGND
V
DV
P
DD
CHARGE
PUMP
MUXOUT
CP