ADF4116 Analog Devices, ADF4116 Datasheet - Page 18

• Manufacturer Part Number: ADF4116
• Description: Single, Integer-n 550 MHZ PLL
• Manufacturer: Analog Devices

ADF4116/ADF4117/ADF4118
APPLICATIONS SECTION
Local Oscillator for GSM Base Station Transmitter
Figure 7 shows the ADF4117/ADF4118 being used with a
VCO to produce the LO for a GSM base station transmitter.
The reference input signal is applied to the circuit at FREF
and, in this case, is terminated in 50 Ω. Typical GSM system
would have a 13 MHz TCXO driving the Reference Input
without any 50 Ω termination. In order to have a channel
spacing of 200 kHz (the GSM standard), the reference input
must be divided by 65, using the on-chip reference divider of
the ADF4117/ADF1118.
The charge pump output of the ADF4117/ADF1118 (Pin 2)
drives the loop filter. In calculating the loop filter component
values, a number of items need to be considered. In this example,
the loop filter was designed so that the overall phase margin for
the system would be 45 degrees. Other PLL system specifica-
tions are given below:
All of these specifications are needed and used to come up with
the loop filter components values shown in Figure 8.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives
the RF Output terminal. A T-circuit configuration provides
50 Ω matching between the VCO output, the RF output and
the RF
In a PLL system, it is important to know when the system is in
lock. In Figure 7, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro-
grammed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
K
K
Loop Bandwidth = 20 kHz
F
N = 4500
Extra Reference Spur Attenuation = 10 dB
REF
D
V
= 12 MHz/V
= 1 mA
IN
= 200 kHz
terminal of the synthesizer.
FREF
IN
1000pF 1000pF
51
8
AV
REF
CE
CLK
DATA
LE
7
V
ADF4117/
3
ADF4118
DD
DD
IN
15
4
MUXOUT
DV
RF
RF
DD
FL
9
16
IN
IN
O
V
CP
V
A
B
P
P
1
14
6
5
2
100pF
100pF
0.15nF
LOCK
DETECT
10k
DECOUPLING CAPACITORS (10 F/10pF) ON AV
ADF4117/ADF4118 AND ON V
OMITTED FROM THE DIAGRAM TO AID CLARITY.
IN
51
1.5nF
27k
3.3k
SHUTDOWN CIRCUIT
The attached circuit in Figure 8 shows how to shut down both
the ADF4116 family and the accompanying VCO. The ADG702
switch goes open circuit when a Logic 1 is applied to the IN
input. The low-cost switch is available in both SOT-23 and
micro SOIC packages.
DIRECT CONVERSION MODULATOR
In some applications a direct conversion architecture can be used
in base station transmitters. Figure 9 shows the combination
available from ADI to implement this solution.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs such as the AD9761
with specified ± 0.02 dB and ± 0.004 dB gain and offset match-
ing characteristics ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The Local Oscillator (LO) is implemented using the ADF4117/
ADF4118. In this case, the OSC 3B1-13M0 provides the stable
13 MHz reference frequency. The system is designed for a
200 kHz channel spacing and an output center frequency of
1960 MHz. The target application is a WCDMA base station
transmitter. Typical phase noise performance from this LO is
–85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is
driven in single-ended fashion. LOIN is ac-coupled to ground
with the 100 pF capacitor and LOIP is driven through the
ac-coupling capacitor from a 50 Ω source. An LO drive level
of between –6 dBm and –12 dBm is required. The circuit of
Figure 9 gives a typical level of –8 dBm.
The RF output is designed to drive a 50 Ω load but must be
ac-coupled as shown in Figure 9. If the I and Q inputs are driven
in quadrature by 2 V p-p signals, the resulting output power will
be around –10 dBm.
620pF
CC
V
VCO190-902T
OF THE VCO190-902T HAVE BEEN
CC
DD
100pF
, DV
DD
100pF
18
, V
P
OF THE
18
18
RF
OUT