lxt9763 Intel Corporation, lxt9763 Datasheet
lxt9763
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lxt9763 Summary of contents
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... A fully independent Media Independent Interface (MII) for each port provides maximum control for switch and multi-port adapter applications. In addition to an expanded set of MDIO registers, the LXT9763 provides three discrete LED driver outputs for each port. The LXT9763 requires only a single 3.3V power supply. ...
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... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT9763 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Preamble Handling..........................................................................34 1.11.2 10T Carrier Sense ..................................................................................34 1.11.3 10T Dribble Bits......................................................................................34 1.11.4 10T Link Test..........................................................................................34 1.12 Monitoring Operations .........................................................................................35 1.12.1 Monitoring Auto-Negotiation...................................................................35 1.12.2 Per-Port LED Driver Functions ...............................................................35 1.13 Boundary Scan (JTAG1149.1) Functions............................................................36 1.13.1 Boundary Scan Interface........................................................................36 1.13.2 State Machine ........................................................................................36 1.13.3 Instruction Register ................................................................................36 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 ...........................................................................................16 3 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 1.13.4 Boundary Scan Register ........................................................................ 37 2.0 Application Information 2.1 Design Recommendations .................................................................................. 38 2.1.1 General Design Guidelines .................................................................... 38 2.1.2 Power Supply Filtering ........................................................................... 38 2.1.3 Power and Ground Plane Layout Considerations .................................. 39 2.1.4 MII Terminations .................................................................................... 39 2.1.5 The RBIAS Pin ....................................................................................... 40 2.1.6 The Twisted-Pair Interface ..................................................................... 40 2.1.7 The Fiber Interface................................................................................. 40 2.2 Typical Application Circuits ................................................................................. 41 3 ...
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... MDIO Write Timing (MDIO Sourced by MAC) ....................................................56 33 MDIO Read Timing (MDIO Sourced by PHY) ....................................................57 34 Power-Up Timing ................................................................................................57 35 RESET And Power-Down Recovery Timing ......................................................58 36 PHY Identifier Bit Mapping .................................................................................64 37 LXT9763 Package Specification .........................................................................73 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 5 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Tables 1 LXT9763 MII Signal Descriptions........................................................................ 11 2 LXT9763 Network Interface Signal Descriptions................................................. 13 3 LXT9763 Miscellaneous Signal Descriptions ...................................................... 13 4 LXT9763 Power Supply Signal Descriptions....................................................... 14 5 LXT9763 JTAG Test Signal Descriptions............................................................ 14 6 LXT9763 LED Signal Descriptions...................................................................... 15 7 Hardware Configuration Settings ...
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... Interrupt Status Register (Address 19, Hex 13) ..................................................70 51 LED Configuration Register (Address 20, Hex 14)..............................................71 52 Transmit Control Register #1 (Address 28).........................................................72 53 Transmit Control Register #2 (Address 30).........................................................72 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 7 ...
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Revision History Revision Date Description ...
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... COLn Detect RX_CLKn RXDn_<3:0> Serial to Parallel RXDVn Converter Carrier Sense CRSn Data Valid Error Detect RX_ERn Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Global Functions Clock Generator Manchester 10 TP OSP Encoder ™ Driver Pulse Scrambler 100 Shaper & ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 2. LXT9763 Pin Assignments GNDD ....... 1 RX_ER4/RXD4_4 ....... 2 TX_ER4/TXD4_4 ....... 3 TX_CLK4 ....... 4 TX_EN4 ....... 5 TXD4_0 ....... 6 TXD4_1 ....... 7 TXD4_2 ....... 8 TXD4_3 ....... 9 COL4 ....... 10 CRS4 ....... 11 RXD3_3 ....... 12 RXD3_2 ....... 13 RXD3_1 ....... 14 VCCIO ....... 15 GNDD ....... 16 RXD3_0 ....... 17 RX_DV3 ....... 18 RX_CLK3 ....... 19 RX_ER3/RXD3_4 ....... 20 TX_ER3/TXD3_4 ....... 21 TX_CLK3 ....... 22 TX_EN3 ....... 23 TXD3_0 ....... 24 TXD3_1 ....... 25 TXD3_2 ....... 26 TXD3_3 ....... 27 COL3 ...
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... RXD0_3 1. Type Column Coding Input Output Open Drain 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit number (0-15). Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 ...
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... RX_CLK4 189 RX_CLK5 1. Type Column Coding Input Output Open Drain 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit number (0-15 Signal Description Receive Data - Port 1 ...
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... RESET I 1. Type Column Coding Input Output Analog. 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit number (0-15). Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 ...
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... N Type Column Coding Input Output Analog. 2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit number (0-15). Table 4. LXT9763 Power Supply Signal Descriptions ...
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... LED/CFG5_3 1. Type Column Coding Input Output Open Drain Open Source. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Signal Description Port 0 LED Drivers 1 -3. These pins drive LED indicators for Port 0. Each LED can display one of several available status conditions as selected by the LED ...
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... This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. On power-up, the LXT9763 reads its configuration pins to check for forced operation settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT9763 auto-negotiates with it using Fast Link Pulse (FLP) bursts ...
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... Table 2 on page 13 The LXT9763 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output. When not transmitting data, the LXT9763 generates 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX, 100-BASE-FX, or 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface ...
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... The LXT9763 supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT9763. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. ...
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... Register 19 provides interrupt status. Setting bit 18 enables a port to request interrupt via the MDINT pin. An active Low on this pin indicates a status change on the LXT9763. However, because shared interrupt, it does not indicate which port is requesting service. Interrupts may be caused by one of four conditions: • ...
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... MII Data Interface The LXT9763 supports six standard MIIs (one per port). The MII consists of a data interface and a management interface. The MII Data Interface passes data between the LXT9763 and one or more Media Access Controllers (MACs). Separate parallel buses are provided for transmit and receive. ...
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... MHz for 100BASE-X operation and at 2.5 MHz for 10BASE-T operation. 1.6 Initialization When the LXT9763 is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as ...
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... The MDIO registers are unaffected. 1.6.2 Reset The LXT9763 provides both hardware and software resets. Configuration control of Auto- Negotiation, speed and duplex mode selection is handled differently for each. During a hardware reset, settings for bits 0.13, 0.12 and 0.8 are read in from the pins (refer to Table 7 on page 23 for pin settings and Table 38 on page 62 for register bit definitions) ...
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... Hardware Configuration Settings The LXT9763 provides a hardware option to set the initial device configuration. The hardware option uses the three LED/CFG pins for each port. This provides three control bits per port, as listed in Table 7. The LED drivers can operate as either open drain or open source circuits as shown ...
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... Auto-Negotiation The LXT9763 attempts to auto-negotiate with its counter-part across the link by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 µ s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be present or absent to indicate a “ ...
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... MII data interface. Separate channels are provided for transmitting data from the MAC to the LXT9763 (TXD), and for passing data received from the line to the MAC (RXD). Each channel has its own clock, data bus, and control signals. Nine signals are used to pass received data to the MAC: RXD< ...
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... Whenever the LXT9763 receives an errored symbol from the network, it asserts RX_ER and drives “1110” on the RXD pins. RX_ER is synchronous with RX_CLK. When the MAC asserts TX_ER, the LXT9763 will drive “H” symbols out on the line. TX_ER must be synchronous with TX_CLK. ...
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... Collision The LXT9763 asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. conditions for assertion of carrier sense, collision, and data loopback signals. ...
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... LXT9763 transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to transmitting Idle symbols. In 100TX mode, the LXT9763 scrambles the data and transmits it to the network using MLT-3 line code. The MLT-3 signals received from the network are descrambled and decoded and sent across the MII to the MAC ...
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... S4 1.10.2 100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT9763 is a Physical Layer 1 (PHY) device. The LXT9763 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u specification. The following paragraphs discuss LXT9763 operation from the reference model point of view ...
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... SSD. Dribble Bits The LXT9763 handles dribbles bits in all modes. If between 1-4 dribble bits are received, the nibble is passed across the MII, padded with 1s if necessary. If between 5-7 dribble bits are received, the second nibble is not sent onto the MII bus Figure 15 ...
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... The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. 3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T /H/ (Error) code group is used to signal an error condition. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 5B Code ...
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... If auto-negotiate is enabled, link failure causes the LXT9763 to re-negotiate. Link Failure Override The LXT9763 normally transmits 100 Mbps data packets or Idle symbols only if the link is up, and transmits only FLP bursts if the link is not up. Setting bit 16. overrides this function, allowing the LXT9763 to transmit data packets even when the link is down. This feature is provided as a diagnostic tool ...
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... Bit 1.4 is set once and clears when read. A far end fault condition causes the LXT9763 to drop the link unless Forced Link Pass is selected (16.14 = 1). Link down condition is then reported via interrupts and status bits. ...
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... LXT9763 are the SFD “5D” hex followed by the body of the packet. In 10T mode with 16 the LXT9763 passes the preamble through the MII and asserts RX_DV and CRS simultaneously. In 10T loopback, the LXT9763 loops back whatever the MAC transmits to it, including the preamble ...
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... Per-Port LED Driver Functions The LXT9763 incorporates three direct drive LEDs per port. On power up all the LEDs will light for approximately 1 second after reset de-asserts. Each LED can be programmed to one of several different display modes using the LED Configuration Register. Each per-port LED can be programmed (refer to • ...
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... Note: The direct drive LED outputs in this diagram are shown as active Low. 1.13 Boundary Scan (JTAG1149.1) Functions LXT9763 includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. 1.13.1 Boundary Scan Interface This interface consists of five pins (TMS,TDI,TDO,TCK and TRST) ...
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... Part ID (hex) 0000 2623 1. The JEDEC 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC (1111 1110) which becomes 111 1110. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Description Capture Shift Update System Function ...
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... Route high-speed signals next to a continuous, unbroken ground plane. • Filter and shield DC-DC converters, oscillators, etc. • Do not route any digital signals between the LXT9763 and the RJ-45 connectors at the edge of the board. • Do not extend any circuit power and ground plane past the center of the magnetics or to the edge of the board ...
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... VCCD and VCCIO pins of the LXT9763. The analog section supplies power to the VCCA pins. The break between the two planes should run underneath the device. In designs with more than one LXT9763, a single continuous analog VCC plane can be used to supply them all. ...
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... Magnetics Information The LXT9763 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit transformers. The transformer isolation voltage should be rated at 1 protect the circuitry from static voltages across the connectors and cables. Refer to requirements. Before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application ...
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... Table 13. Magnetics Requirements Parameter Return Loss Rise Time 2.2 Typical Application Circuits Figure 18 shows a typical layout of the LXT9763 twisted-pair interface in a dual-high (stacked) RJ-45 application. Figure 17. Power and Ground Supply Connections LXT9763 GNDS RBIAS GNDA VCCT VCCR VCCD GNDD VCCIO Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 18. Typical Twisted-Pair Interface A LXT9763 1. The 100Ω transmit load termination resistor typically required is integrated in the LXT97xx. 2. Magnetics without a receive pair center-tap do not require termination. 3. Center tap current may be supplied from 3.3V VCCA as shown. However, additional power savings may be realized by supplying the center-tap from from a 2 ...
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... TPFON n TPFOP n LXT9763 TPFIN n TPFIP n 1. Refer to fiber transceiver manufacturer’s recommendations for termination circuitry. Example shown above is suitable for HFBR5900-series devices. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 VCCD +3.3V 16 Ω Ω GNDD Fiber Txcvr ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 3.0 Test Specifications Table 14 through Table 34 Note: specifications of the LXT9763. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in recommended operating conditions specified in Table 14. Absolute Maximum Ratings Parameter Supply voltage Operating temperature ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100 Ω (+/-1%) resistor. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 1 Sym ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 20. 100BASE-FX Transceiver Characteristics Parameter Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially) Peak differential input voltage Common mode input range 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. ...
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... Receive start of “J” to COL asserted Receive start of “T” to COL de-asserted 6. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 0ns t4 t3 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 21. 100BASE-TX Transmit Timing (4B Mode) 0ns TX_CLK TX_EN TXD<3:0> TPFO CRS Table 23. 100BASE-TX Transmit Timing Parameters (4B Mode) Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High ...
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... Receive start of “J” to COL asserted Receive start of “T” to COL de-asserted 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 0ns 0ns t4 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 23. 100BASE-TX Transmit Timing (5B Mode) 0ns TX_CLK TX_EN TXD<4:0> TPFO CRS Table 25. 100BASE-TX Transmit Timing Parameters (5B Mode) Parameter TXD<4:0>, TX_EN, TX_ER setup to TX_CLK High TXD<4:0>, TX_EN, TX_ER hold from TX_CLK High ...
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... Receive start of “J” to COL asserted Receive start of “T” to COL de-asserted 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 0ns t4 t3 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 25. 100BASE-FX Transmit Timing 0ns TXCLK TX_EN TXD<3:0> t5 TPFO t3 CRS Table 27. 100BASE-FX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted ...
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... TPFI quiet to COL de-asserted 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. CRS is asserted. RXD/RX_DV are driven at the start of SFD (64 BT). Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 27. 10BASE-T Transmit Timing TX_CLK t 1 TXD, TX_EN, TX_ER t 3 CRS TPFO Table 29. 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Figure 30. Auto Negotiation and Fast Link Pulse Timing Clock Pulse TPFOP t1 Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Sym Min Typ t1 0.65 – ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 31. Fast Link Pulse Timing FLP Burst TPFOP t4 Table 32. Auto Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width ...
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... Table 34. Power-Up Timing Parameters Parameter Voltage threshold Power Up delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 t3 1 Sym Min Typ ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Figure 35. RESET And Power-Down Recovery Timing RESET MDIO,etc Table 35. RESET and Power-Down Recovery Timing Parameters Parameter RESET pulse width RESET recovery delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. ...
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... LED Configuration Register 21-27 Reserved 28 Transmit Control Register #1 29 Reserved 30 Transmit Control Register #2 31 Reserved Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Table 37 for a complete bit map. Table 38 Register Name Table 36 for a complete through Table 53 provide Bit Assignments Refer to ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII 60 Datasheet ...
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... Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 61 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 38. Control Register (Address 0) Bit Name 1 = PHY reset. 0.15 Reset 0 = Normal operation Enable loopback mode. 0.14 Loopback 0 = Disable loopback mode. 0.6 1 0.13 Speed Selection Auto-Negotiation 1 = Enable Auto-Negotiation Process. 0.12 3 Enable 0 = Disable Auto-Negotiation Process Power-down. 0.11 Power-Down 0 = Normal operation ...
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... Bit 1.4 is not valid if Auto-Negotiation is selected while operating in Fiber mode. Table 40. PHY Identification Register 1 (Address 2) Bit Name PHY ID 2.15:0 The PHY identifier composed of bits 3 through 18 of the OUI. Number Read Only. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Description Description 1 Type Default ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 41. PHY Identification Register 2 (Address 3) Bit Name The PHY identifier composed of bits 19 through 24 of the 3.15:10 PHY ID number OUI. Manufacturer’s 3.9:4 6 bits containing manufacturer’s part number. model number Manufacturer’s 3.3:0 4 bits containing manufacturer’s revision number. ...
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... Table 42. Auto Negotiation Advertisement Register (Address 4) (Continued) Bit Name 1 = 100BASE-T4 capability is available 100BASE-T4 capability is not available. (The LXT9763 does not support 100BASE-T4 but allows this bit to be set to 4.9 100BASE-T4 advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 43. Auto Negotiation Link Partner Base Page Ability Register (Address 5) (Continued) Bit Name 10BASE Link Partner is 10BASE-T full-duplex capable. 5 Link Partner is not 10BASE-T full-duplex capable. full-duplex 1 = Link Partner is 10BASE-T capable. 5.5 10BASE Link Partner is not 10BASE-T capable. < ...
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... Link Partner has no additional next pages to send. Acknowledge 1 = Link Partner has received Link Code Word from LXT9763 8.14 (ACK Link Partner has not received Link Code Word from LXT9763. Message Page 1 = Page sent by the Link Partner is a Message Page. 8.13 (MP Page sent by the Link Partner is an Unformatted Page. ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 47. Port Configuration Register (Address 16, Hex 10) Bit Name 16.15 Reserved Write as zero, ignore on read Force Link Pass. Sets appropriate registers, state machines and 16.14 Force Link Pass LEDs to Pass condition, regardless of actual link state. ...
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... Do not allow event to cause interrupt. Mask for Link Status Interrupt. 18.4 LINKMSK 1 = Enable event to cause interrupt not allow event to cause interrupt. 18.3 Reserved Write as zero, ignore on read. 1. R/W = Read /Write. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Description Description 1 Type Default ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 49. Interrupt Enable Register (Address 18, Hex 12) (Continued) Bit Name 18.2 Reserved Write as 0, ignore on read. Interrupt Enable. 18.1 INTEN 1 = Enable interrupts on this port Disable interrupts on this port. Test Interrupt. 18.0 TINT 1 = Force interrupt on MDINT. ...
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... Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Duplex LED maybe active for a brief time after loss of link. Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 Description 5 2 ...
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... LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII Table 51. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name 00 = Stretch LED events Stretch LED events to 60 ms. 20.3:2 LEDFREQ 10 = Stretch LED events to 100 ms Reserved. 20.1 PULSE Disable pulse stretching of all LEDs. ...
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... Figure 37. LXT9763 Package Specification 208-Pin Plastic Quad Flat Package • Part Number LXT9763HC • Commercial Temperature Range (0 ° ° Datasheet Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763 θ θ θ 3 ...
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