sza1000 NXP Semiconductors, sza1000 Datasheet - Page 11

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sza1000

Manufacturer Part Number
sza1000
Description
Qic Digital Equalizer
Manufacturer
NXP Semiconductors
Datasheet

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Control register functions
Control register functions are detailed in Tables 2 to 43.
FIR
Addresses 0 to 9: FIR tap coefficient values
Table 2 Coefficient values: FIR_VAL0 to FIR_VAL9; note 1
Note
1. These are 7-bit coefficient values in two’s complement notation; taps 5 to 9 are only used when R = 2; tap 10 has a
Addresses 10 to 15: FIR tap position selection
Table 3
Note
1. See Table 4 for the value of FSn.n.
1998 Feb 16
ADDRESS
QIC digital equalizer
ADDR.
fixed coefficient value of +64.
FUNCTION
D7
35
36
37
38
39
40
41
42
43
44
45
10
11
12
13
14
15
Tap position selection: FIR_SELnn; note 1
FIR_VALn.6
FIR_SEL05
FIR_SEL16
FIR_SEL27
FIR_SEL38
FIR_SEL49
FIR_SEL10
NAME
D6
PLL_FREQH
PLL_FREQL
EQ_MODE1
WIN_SHIFT
EQ MODE0
STRIPE_F
MLD_SET
CLK_DIV
PLL_NP
PLL_NI
NAME
DIFF
FIR_VALn.5
0 and 5
1 and 6
2 and 7
3 and 8
4 and 9
TAPS
D5
10
Mode setting for PACLK (pin 29) and GAP/STRIPE (pin 21)
(see Tables 21, 22 and 23)
differentiator settings (see Tables 24, 25 and 26)
main clock divider (see Tables 27 and 28)
stripe detector nominal frequency (see Table 29)
equalizer mode settings
PLL nominal frequency bits 0 to 7
PLL nominal frequency bits 8 to 10
PLL window shift
PLL loop filter integrating gain and range
PLL loop filter proportional gain
maximum likelihood detector settings
FIR_VALn.4
D7
D4
D6
11
FIR_VALn.3
FS0.2
FS1.2
FS2.2
FS3.2
FS4.2
D3
D5
DESCRIPTION
FS0.1
FS1.1
FS2.1
FS3.1
FS4.1
FIR_VALn.2
D4
D2
FS10.3 FS10.2 FS10.1 FS10.0
FS0.0
FS1.0
FS2.0
FS3.0
FS4.0
D3
FIR_VALn.1
FS5.2
FS6.2
FS7.2
FS8.2
FS9.2
D2
D1
Product specification
FS5.1
FS6.1
FS7.1
FS8.1
FS9.1
SZA1000
D1
FIR_VALn.0
D0
FS5.0
FS6.0
FS7.0
FS8.0
FS9.0
D0

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