sza1000 NXP Semiconductors, sza1000 Datasheet - Page 20

• Manufacturer Part Number: sza1000
• Description: Qic Digital Equalizer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Address 42: Phase comparator window shift
WIN_SHIFT is an 8-bit number in two’s complement format. The programmed phase shift is 180
Address 43: PLL settings
Table 37 Address 43: PLL_NI; note 1
Note
1. If LTD (pin 19) is HIGH, NI2 is selected, else NI1.
Table 38 DL setting; note 1
Note
1. The Differentiator Delay (DL) settings (see Table 25) determine the values of Q1 and Q0 that should be entered.
Table 39 Integrating gain factor KI
Address 44: PLL loop filter proportional gain
Table 41 PLL_NP; note 1
Note
1. If LTD (pin 19) is HIGH, NP2 is selected, else NP1.
1998 Feb 16
QIC digital equalizer
Q1
D7
D7
DL SETTING
NI
0
1
2
3
DL1 = DL2
DL1 < DL2
DL1 > DL2
Q0
D6
D6
RNG.1
NP2.2
D5
D5
1
1
1
1
KI
128
256
512
64
RNG.0
NP2.1
D4
D4
Q1
20
1
1
0
Table 40 PLL range
NP2.0
NI2.1
D3
D3
RNG
0
1
2
3
NP1.2
NI2.0
D2
D2
NP1. 1
NI1.1
D1
D1
WIN_SHIFT degrees.
Q0
PLL RANGE
Product specification
1
0
1
SZA1000
128
256
512
64
NP1. 0
NI1.0
D0
D0