sza1000 NXP Semiconductors, sza1000 Datasheet - Page 19

• Manufacturer Part Number: sza1000
• Description: Qic Digital Equalizer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 31 FIR/LPF Sample Rate
Table 34 Mode settings: pins 25, 27 and AUXBUS
Notes
1. QUAL is a test signal (active HIGH) used to detect valid signal peaks (see also Table 22).
2. When COMP is selected, pin 25 is switched to the output of the read pulse circuit comparator for test purposes.
PLL
Addresses 40 and 41: PLL nominal frequency
Table 35 PLL_FREQL (address 40)
Table 36 PLL_FREQH (address 41); note 1
Note
1. The nominal PLL frequency is
1998 Feb 16
QIC digital equalizer
FUNCTIONS
ST
10
12
13
14
15
PF.7
11
0
1
2
3
4
5
6
7
8
9
D7
D7
R1
0
1
Reduction Factor: R
PLL on, peak-to-peak level output
PLL on, PLL frequency output
PLL on, differentiator output
PLL on, filtered level output
PLL on, PLL phase output
PF.6
D6
D6
PLL off, AD bypass
PLL off, AD bypass
PLL on, AD bypass
PLL on, LPF output
PLL on, FIR output
one shot test
IC MODE
ADC test
DAC test
2
1
R
PLL off
PLL off
PLL on
PF.5
f
s
D5
D5
------------ -
2048
PF
Table 32 DAC power
STBY1
0
1
PF.4
D4
D4
PIN 27
SRD
SRD
SRD
SRD
SRD
SRD
SRD
SRD
SRD
SRD
RD
RD
RD
RD
RD
19
D/A POWER
COMP
PF.3
QUAL
D3
D3
PIN 25
COMP
COMP
QUAL
RRC
RRC
RRC
RRC
RRC
RRC
RRC
RRC
RRC
RRC
on
off
(1)
(2)
FIR output after scaling and interpolator
bits 7 to 1: LEVEL_ABS; bit 0:WDOUT
bits 7 to 1: LEVEL_FIL; bit 0:WDOUT
PF.10
PF.2
D2
D2
differentiator output after scaling
bit 0: WDOUT, bits 1 to 7 high-Z
bit 0: WDOUT, bits 1 to 7 high-Z
bit 0: WDOUT, bits 1 to 7 high-Z
Table 33 ADC power
LPF output after scaling
PLL phase error output
PLL frequency output
STBY2
8-bit input to HPF
8-bit input to HPF
8-bit input to HPF
0
1
ADC output
DAC output
AUXBUS
PF.1
PF.9
D1
D1
Product specification
SZA1000
A/D POWER
on
off
PF.0
PF.8
D0
D0