sza1000 NXP Semiconductors, sza1000 Datasheet - Page 21

• Manufacturer Part Number: sza1000
• Description: Qic Digital Equalizer
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 42 Proportional gain factor KP
M
Address 45: Settings
Table 43 Address 45: MLD_SET
Notes
1. Check for k constraint: k is the maximum number of channel bit-cells allowed without a transition. For MFM code:
2. Check for d = 1 constraint: d is the minimum number of channel bit-cells without transitions that must come between
3. Check partial response constraints; delete incorrect peaks.
4. Check partial response constraints; add missing peaks.
5. ks = k + 1.
S
The status register contains 5 status bytes. The contents of the status bytes can be read via the serial interface.
Table 44 Status bytes; notes 1 to 4
Notes
1. The levels are measured behind the re-sampling block (interpolator) (see Fig.1).
2. Actual PLL frequency is an 8-bit unsigned number:
3. LEVEL_FIL can be used for reading of the burst levels, or in an AGC loop (with the TZA1000 preamplifier).
4. LEVEL_POS, LEVEL_NEG, LEVEL_ABS and LEVEL_FIL are 8-bit numbers in two’s complement format.
1998 Feb 16
TATUS REGISTER
AXIMUM LIKELIHOOD DETECTOR FUNCTIONS
ADDRESS
QIC digital equalizer
en_k
k = 3 (ks = 4), for RLL(1,7) code: k = 7 (ks = 8).
two bit cells with transitions. d = 1 for both MFM and RLL(1,7) codes
255
255
255
255
255
D7
(1)
DATA
en_d
0
1
2
3
4
D6
NP
0
1
2
3
4
5
6
7
(2)
LEVEL_POS
LEVEL_NEG
LEVEL_ABS
LEVEL_FIL
NAME
FREQ
PR1
D5
(3)
PR0
D4
(4)
f
s
21
FREQ
----------------- -
256
ks3
negative peaks in measured level
D3
positive peaks in measured level
low-pass filtered LEVEL_ABS
(5)
measured peak-to-peak level
actual frequency of PLL
DESCRIPTION
ks2
D2
KP
1
1
1
1
1
1
16
32
2
4
8
(5)
ks1
D1
(5)
Product specification
SZA1000
ks0
D0
(5)