ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 151

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272M
24.8.15
Note:
24.8.16
Table 70.
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
5
6
7
8
9
10
11
12
13
14
15
16
CC ALE high time
CC Address setup to ALE
CC Address hold after ALE
tCC
CC
CC
CC
CC
CC
SR
SR
SR
ALE falling edge to RD, WR
(with RW-delay)
ALE falling edge to RD, WR
(no RW-delay)
Address float after RD, WR (with
RW-delay)1
Address float after RD, WR
(no
RD, WR low time
(with RW-delay)
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
(no RW-delay)
(with RW-delay)
(no RW-delay)
Table 69.
External memory bus timing
The following sections include the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40 MHz.
All External Memory Bus Timings and SSC Timings listed in the following tables are granted
by Design Characterization and not fully tested in production.
Multiplexed bus
V
ALE cycle time = 6 TCL + 2t
Multiplexed bus timings
RW-delay)1
ALE Extension
Memory Cycle Time wait states
Memory Tri-state Time
DD
= 5V ± 10%, V
Parameter
Description
Memory cycle variables
SS
= 0V, T
– 8.5 + t
15.5 + t
A
1.5 + t
28 + t
A
4 + t
4 + t
4 + t
+ t
Min
= -40 to +125°C, CL = 50pF,
–
–
–
–
–
f
TCL = 12.5ns
C
CPU
A
A
A
C
A
+ t
C
A
= 40 MHz
F
Symbol
(75ns at 40 MHz CPU clock without wait states)
18.5 + t
+ t
t
t
t
17.5 +
6 + t
A
C
F
Max
18.5
A
–
–
–
–
–
6
–
–
+ t
C
C
C
TCL x [ALECTL]
2TCL x (15 - [MCTC])
2TCL x (1 - [MTTC])
2TCL – 9.5 + t
3TCL – 9.5 + t
TCL – 8.5 + t
TCL – 8.5 + t
TCL – 8.5 + t
TCL – 11 + t
– 8.5 + t
Min
1/2 TCL = 1 to 40 MHz
–
–
–
–
–
Variable CPU clock
A
A
Electrical characteristics
A
A
A
C
C
Values
2TCL – 19 + t
3TCL – 19 + t
3TCL – 20 +
+ t
TCL + 6
Max
A
–
–
–
–
–
6
–
–
+ t
C
C
C
151/176
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns