ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 63

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272M
13
13.1
13.2
13.2.1
Parallel ports
Introduction
The ST10F272M MCU provides up to 111 I/O lines with programmable features. These
capabilities permit this MCU to be adapted to a wide range of applications.
ST10F272M has nine groups of I/O lines gathered as follows:
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These ports may be used as general purpose bidirectional input or output, software
controlled with dedicated registers.
For example, the output drivers of six of the ports (2, 3, 4, 6, 7, 8) can be configured
(bitwise) for push-pull or open drain operation using ODPx registers.
The input threshold levels are programmable (TTL/CMOS) for all the ports. The logic level of
a pin is clocked into the input latch once per state time, regardless whether the port is
configured for input or output. The threshold is selected with PICON and XPICON registers
control bits.
A write operation to a port pin configured as an input causes the value to be written into the
port output latch, while a read operation returns the latched state of the pin itself. A read-
modify-write operation reads the value of the pin, modifies it, and writes it back to the output
latch.
Writing to a pin configured as an output (DPx.y = ‘1’) causes the output latch and the pin to
have the written value, since the output buffer is enabled. Reading this pin returns the value
of the output latch. A read-modify-write operation reads the value of the output latch,
modifies it, and writes it back to the output latch, thus also modifying the level at the pin.
I/O lines support an alternate function which is detailed in the following description of each
port.
I/O’s special features
Open drain mode
Some of the I/O ports of ST10F272M support the open drain capability. This programmable
feature may be used with an external pull-up resistor, in order to provide an AND wired
logical function.
This feature is implemented for ports P2, P3, P4, P6, P7 and P8 (see respective sections),
and is controlled through the respective Open Drain Control Registers ODPx.
Port 0 is a two time 8-bit port named P0L (low as less significant byte) and P0H (high
as most significant byte)
Port 1 is a two time 8-bit port named P1L and P1H
Port 2 is a 16-bit port
Port 3 is a 15-bit port (P3.14 line is not implemented)
Port 4 is an 8-bit port
Port 5 is a 16-bit port input only
Port 6, Port 7 and Port 8 are 8-bit ports
Parallel ports
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