ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 157

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272M
24.8.17
Table 71.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
5
6
80
81
12
13
14
15
16
17
18
20
21
22
24
26
28
28h
38
CC ALE high time
CC Address setup to ALE
CC
CC
CC
CC
SR
SR
SR ALE low to valid data in
SR
SR
SR
SR
CC Data valid to WR
CC Data hold after WR
CC ALE rising edge after RD, WR
CC
CC
CC
Address/Unlatched CS setup
to RD, WR
(with RW-delay)
Address/Unlatched CS setup
to RD, WR
(no RW-delay)
RD, WR low time
RD, WR low time
RD to valid data in
RD to valid data in
Address/Unlatched CS to
valid data in
Data hold after RD
rising edge
Data float after RD rising
edge (with RW-delay)
Data float after RD rising
edge (no RW-delay)
Address/Unlatched CS hold
after RD, WR
Address/Unlatched CS hold
after WRH
ALE falling edge to Latched
CS
(with RW-delay)
(no RW-delay)
(with RW-delay)
(no RW-delay)
Demultiplexed bus
V
ALE cycle time = 4 TCL + 2t
Demultiplexed bus timings
DD
.
= 5V ± 10%, V
Parameter
(2)
(1)
(1)
SS
= 0V, T
12.5 + 2t
0.5 + 2t
15.5 + t
1.5 + t
-10 + t
28 + t
10 + t
A
-5 + t
4 + t
-4 - t
4 + t
0 + t
A
Min
+ t
–
–
–
–
0
–
–
= -40 to +125°C, CL = 50pF,
f
TCL = 12.5ns
CPU
C
A
F
F
A
F
C
C
A
F
C
A
+ t
A
= 40 MHz
F
(50ns at 40 MHz CPU clock without wait states).
17.5 + t
20 + 2t
18.5 + t
16.5 + t
6 + t
4 + t
6 - t
Max
+ t
+ t
–
–
–
–
–
–
–
–
–
–
–
–
C
C
A
C
F
A
A
C
F
+
+
2TCL - 9.5 + t
3TCL - 9.5 + t
TCL - 12 + 2t
2TCL - 15 + t
TCL - 8.5 + t
2TCL - 12.5 +
TCL - 8.5 + t
TCL - 11 + t
-10 + t
-5 + t
-4 - t
0 + t
+ 2t
1/2 TCL = 1 to 40 MHz
Min
Variable CPU clock
–
–
–
–
0
–
–
A
F
A
F
F
A
Electrical characteristics
A
F
C
A
C
C
2TCL - 19 + t
3TCL - 19 + t
2TCL - 8.5 +
3TCL - 20 +
4TCL - 30 +
TCL - 8.5 +
+ 2t
+ t
+ t
+ t
6 - t
Max
F
F
A
A
–
–
–
–
–
–
–
–
–
–
–
–
+ 2t
+ 2t
+ t
+ t
A
C
A
A
C
C
C
157/176
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns