ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 168

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ST10F272M-4Q3

Manufacturer Part Number
ST10F272M-4Q3
Description
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Electrical characteristics
24.8.20.2 Slave mode
Table 75.
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
2. Formula for SSC Clock Cycle time: t
168/176
t
t
t
t
t
t
t
t
t
t
t
Symbol
310
311
312
313
314
315
316
317p
318p
317
318
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after
checking that resulting timings are suitable for the master).
Where <SSCBR> represents the content of the SSC baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
CC Write data valid after shift edge
CC Write data hold after shift edge
SR SSC clock cycle time
SR SSC clock high time
SR SSC clock low time
SR SSC clock rise time
SR SSC clock fall time
SR
SR
SR
SR
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
V
SSC slave mode timings
DD
= 5V ±10%, V
Parameter
310
is 125ns (corresponding to 8Mbaud).
(2)
SS
310
= 0V, T
= 4 TCL * (<SSCBR> + 1)
A
= -40 to +125°C, C
(<SSCBR> = 0002h)
Maximum baudrate
Min
150
63
63
62
87
31
@ f
0
6
6.6 Mbaud
CPU
= 40 MHz
(1)
Max
150
10
10
55
L
= 50pF
(<SSCBR> = 0001h - FFFFh)
t
t
4TCL + 12
6TCL + 12
310
310
2TCL + 6
8TCL
Min
/ 2 - 12
/ 2 - 12
Variable baudrate
0
6
262144 TCL
2TCL + 30
Max
10
10
ST10F272M
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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