SC92031L SILAN [Silan Microelectronics Joint-stock], SC92031L Datasheet - Page 10

• Manufacturer Part Number: SC92031L
• Description: 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER
• Manufacturer: SILAN [Silan Microelectronics Joint-stock]

3 Interrupt Status Register (Offset 000Ch, R)
mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.
4 Interrupt Mask Register (Offset 0010h, R/W)
5 Receive Buffer Start Address Register (Offset 0014h, R/W)
6 TX_STATUS: Transmit Status of All Descriptors (Offset 001Ch, R)
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31-16
28-7
28-7
31-0
4-1
Bit
4-1
31
30
29
Bit
Bit
The interrupt Status Register reflects all current pending interrupts, regardless of the state of the corresponding
31
30
29
Bit
15
14
13
12
11
10
6
5
0
6
5
0
9
8
7
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
-
-
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
-
-
-
Link fail
Link OK
Time Out
-
Rx Buffer Overflow Receive Buffer Overflow
Rx OK
-
Tx OK
Link fail
Link OK
Time Out
-
Rx Buffer Overflow Receive Buffer Overflow: 1 => Enable, 0 => Disable.
Rx OK
-
Tx OK
RBSTART
-
TOK3
TOK2
TOK1
TOK0
TUN3
TUN2
TUN1
TUN0
TABT3
Symbol
Symbol
Symbol
Symbol
Link Status is changed to Failure
Link Status is changed to Success
Time Out: Set to 1 when the TCTR register reaches to the value of the
TimerInt register.
Reserved
Receive OK
Reserved
Transmit OK
Receive Buffer Start Address
Link Fail Interrupt: 1 => Enable, 0 => Disable.
Link OK Interrupt: 1 => Enable, 0 => Disable.
Time Out Interrupt: 1 => Enable, 0 => Disable.
Reserved
Receive OK Interrupt: 1 => Enable, 0 => Disable.
Reserved
Transmit OK Interrupt: 1 => Enable, 0 => Disable.
Reserved
TOK bit of Descriptor3
TOK bit of Descriptor2
TOK bit of Descriptor1
TOK bit of Descriptor0
TUN bit of Descriptor3
TUN bit of Descriptor2
TUN bit of Descriptor1
TUN bit of Descriptor0
TABT bit of Descriptor3
Description
Description
Description
Description
REV:1.0
SC92031
(To be continued)
Page 10 of 38
2004.08.03