SC92031L SILAN [Silan Microelectronics Joint-stock], SC92031L Datasheet - Page 24

• Manufacturer Part Number: SC92031L
• Description: 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER
• Manufacturer: SILAN [Silan Microelectronics Joint-stock]

Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set.
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Status: The status register is a 16-bit register used to record status information for PCI bus related events.
15-10
Bit
9
8
7
6
5
4
3
2
1
0
VGASNOOP
SERREN
PERRSP
SCYCEN
ADSTEP
FBTBEN
Symbol
MEMEN
MWIEN
BMEN
IOEN
-
Reserved
Fast Back-To-Back Enable: When <FBTBEN>=0, read as a zero. write operation
has no effect. The SC92031 will not generate Fast Back-to-back cycles. When
<FBTBEN>=1, This read/write bit controls whether or not a master can do fast
back-to-back transactions to different devices. Initialization software will set the bit
if all targets are fast back-to-back capable. A value of one means the master is
allowed to generate fast back-to-back transaction to different agents. A value of
zero means fast back-to-back transactions are only allowed to the same agent.
This bit’ s state after RSTB is zero.
System Error Enable: When set a one, the SC92031 drive the SERRB line when it
detects a parity error on the address phase (AD<31:0> and CBEB<3:0> ); A zero
disables the SC92031’ s SERRB output driver.
Address/Data Stepping: Read as zero, write operation has no effect. The
SC92031 disable to perform address/data stepping.
Parity Error Response: When set to a one, the SC92031 will assert the PERRB pin
on the detection of a data parity error when acting as the target, and will sample
the PERRB pin as the master. When cleared to a zero, any detected parity error is
ignored and the SC92031 continues normal operation.
Parity checking is disabled after hardware reset (RSTB).
VGA palette SNOOP: Read as a zero, write operation has no effect.
Memory Write and Invalidate cycle Enable: Read as a zero, write operation has no
effect.
Special Cycle Enable: Read as a zero, write operation has no effect. The
SC92031 ignores all special cycle operation.
Bus Master Enable: When set to a one, the SC92031 is capable of acting as a bus
master. When cleared to a zero, it is prohibited from acting as a PCI bus master.
For the normal operation, this bit must be set by the system BIOS.
Memory Space Access: When set to a one, the SC92031 responds to memory
space accesses. When cleared to a zero, the SC92031 ignores memory space
accesses.
I/O Space Access: When set to a one, the SC92031 responds to I/O space
access. When cleared to a zero, the SC92031 ignores I/O space access.
Description
REV:1.0
SC92031
Page 24 of 38
2004.08.03