SC92031L SILAN [Silan Microelectronics Joint-stock], SC92031L Datasheet - Page 7

• Manufacturer Part Number: SC92031L
• Description: 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER
• Manufacturer: SILAN [Silan Microelectronics Joint-stock]

(Continued)
REGISTER DESCRIPTION
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
The chip provides the following set of operational registers mapped into PCI memory space or I/O space.
Offset
0x0C
0x1C
0x2C
0x3C
0x4C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x54
0x58
Pin No.
50
80
56
57
68
77
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
-
ANTEST_A
ANTEST_B
PORXRS
Symbol
G_RST
CLKR
SE
CONFIG0
CONFIG1
RBW_PTR
INT_STATUS
INT_MASK
RBSA
RBR_PTR
TX_STATUS
TX_ STATUS0
TX_ STATUS1
TX_ STATUS2
TX_ STATUS3
TX_ADDR0
TX_ADDR1
TX_ADDR2
TX_ADDR3
RX_CONFIG
MAC_ADDR0
MAC_ADDR1
MULTI_GROUP0
MULTI_GROUP1
RX_STATUS0
-
Tag
Clock run for PCI system. In normal operation situation, Host should assert
this signal to indicate SC92031 about the normal situation. On the other
hand, when the host will dessert this signal when the clock is going down to
a non-operating frequency. When SC92031 recognizes the de-asserted
status of clockrun, then it will assert clockrun to request host to maintain the
normal clock operation. When clockrun function is disabled then the
SC92031 will set clockrun in tri-state.
Scan chain test enable
Analog test pin
Power on reset output
Global reset input pin
Bit Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Software Reset
Select Rx Buffer Size
Rx buffer write pointer
Interrupt status register
Interrupt mask register
Rx buffer start address
Rx buffer read pointer
Transmit Status of All Descriptors
Transmit Status of Descriptor 0
Transmit Status of Descriptor 1
Transmit Status of Descriptor 2
Transmit Status of Descriptor 3
Transmit Start Address of Descriptor 0
Transmit Start Address of Descriptor 1
Transmit Start Address of Descriptor 2
Transmit Start Address of Descriptor 3
Receive Configuration Register
MAC Address 0
MAC Address 1
Multicast Group 0
Multicast Group 1
Receive Status Register 0
Reserved
Description
Description
REV:1.0
SC92031
(To be continued)
Page 7 of 38
2004.08.03