SC92031L SILAN [Silan Microelectronics Joint-stock], SC92031L Datasheet - Page 5

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SC92031L

Manufacturer Part Number
SC92031L
Description
10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER
Manufacturer
SILAN [Silan Microelectronics Joint-stock]
Datasheet
(Continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
Power Management/Isolation Interface
EEPROM Interface
EEPROM Interface
98, 10, 20, 31
Pin No.
14
11
85
86
99
81
12
13
19
16
18
15
87
71
49
47
46
45
48
DEVSELB
C/BE3-0B
FRAMEB
Symbol
PERRB
SERRB
LWAKE
TRDYB
STOPB
IRDYB
INTAB
REQB
IDSEL
EEDO
GNTB
PMEB
EECK
EECS
EEDI
PAR
AUX
PCI bus command and byte enables.
Device Select, target is driving to indicate the address is decoded.
Begin and duration of bus access, driven by master device.
PCI bus granted. This signal indicates that the PCI bus request of SC92031
has been accepted.
PCI bus request, the SC92031 will assert this signal low to request the
ownership of the bus from the central arbiter.
Initialization Device Select. This pin allows the SC92031 to identify when
configuration read/write transactions are intended for it.
PCI interrupt request. It is asserted low when an interrupt condition occurs,
as defined by the Interrupt Status, Interrupt Mask and Interrupt Enable
registers.
Master device is ready to data transaction.
Slave device is ready to data transaction.
Parity, this signal indicates even parity across AD31-0 and C/BE3-0
including the PAR pin. As a master, PAR is asserted during address and
write data phases. As a target, PAR is asserted during read data phases.
Data parity error is detected, driven by the agent receiving data.
Address parity error.
The current target is requesting the master to stop the current transaction.
Power Management Event, Open drain, active low. Used by the SC92031 to
request a change in its current power management state and/or to indicate
that a power management event has occurred.
LAN WAKE-UP signal, This signal is used to inform the motherboard to
execute the wake-up process. The motherboard must support Wake-On-
LAN (WOL). There are 4 choices of output, including active high, active low,
positive pulse, and negative pulse, that may be asserted from the LWAKE
pin.
This pin is used to notify the SC92031 of the existence of Aux. power during
initial power-on or a PCI reset. This pin should be pulled high to the Aux.
power via a resistor to detect the Aux. power. Doing so, will enable wakeup
support from ACPI D3 cold or APM power-down. If this pin is not pulled
high, the SC92031 assumes that no Aux. power exists.
EEPROM chip serial clock
EEPROM chip serial data in
EEPROM chip serial data out
EEPROM chip select
Description
REV:1.0
SC92031
(To be continued)
Page 5 of 38
2004.08.03

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