SC92031L SILAN [Silan Microelectronics Joint-stock], SC92031L Datasheet - Page 25

• Manufacturer Part Number: SC92031L
• Description: 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER
• Manufacturer: SILAN [Silan Microelectronics Joint-stock]

RID: Revision ID Register
PIFR: Programming Interface Register
SC92031 controller. Because the PCI version 2.1 specification does not define any specific value for network
devices, PIFR = 00h.
SCR: Sub-Class Register
the SC92031 is an Ethernet controller.
BCR: Base-Class Register
indicates that the SC92031 is a network controller.
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The Revision ID register is an 8-bit register that specifies the SC92031 controller revision number.
The programming interface register is an 8-bit register that identifies the programming interface of the
The Sub-class register is an 8-bit register that identifies the function of the SC92031. SCR = 00h indicates that
The Base-class register is an 8-bit register that broadly classifies the function of the SC92031. BCR = 02h
10-9
3-0
Bit
15
14
13
12
11
8
7
6
5
4
NewCap
Symbol
DPERR
RMABT
SSERR
DST1-0
RTABT
STABT
66MHz
FBBC
DPD
UDF
-
Detected Parity Error: When set indicates that the SC92031 detected a parity error,
even if parity error handling is disabled in command register PERRSP bit.
Signaled System Error: When set indicates that the SC92031 asserted the system
error pin, SERRB. Writing a one clears this bit to zero.
Received Master Abort: When set indicates that the SC92031 terminated a master
transaction with master abort. Writing a one clears this bit to zero.
Received Target Abort: When set indicates that the SC92031 master transaction
was terminated due to a target abort. Writing a one clears this bit to zero.
Signaled Target Abort: Set to a one whenever the SC92031 terminates a
transaction with target abort. Writing a one clears this bit to zero.
Device Select Timing: These bits encode the timing of DEVSELB. They are set to
01b (medium), indicating the SC92031 will assert DEVSELB two clocks after
FRAMEB is asserted.
Data Parity error Detected:
This bit sets when the following conditions are met:
Ø
Ø
Ø
Writing a one clears this bit to zero.
Fast Back-To-Back Capable: <FBTBEN>=0, Read as zero, write operation has no
effect. <FBTBEN>=1, Read as one.
User Definable Features Supported: Read as zero, write operation has no effect.
The SC92031 does not support UDF.
66 MHz Capable: Read as zero, write operation has no effect. The SC92031 has
no 66MHz capability.
New Capability: <PMEN>=0, Read as zero, write operation has no effect.
<PMEN>=1, Read as one.
Reserved
The SC92031 asserts parity error (PERRB pin) or it senses the assertion of
PERRB pin by another device.
The SC92031 operates as a bus master for the operation that caused the
error.
The Command register PERRSP bit is set.
Description
REV:1.0
SC92031
Page 25 of 38
2004.08.03