SC92031L SILAN [Silan Microelectronics Joint-stock], SC92031L Datasheet - Page 19

• Manufacturer Part Number: SC92031L
• Description: 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER
• Manufacturer: SILAN [Silan Microelectronics Joint-stock]

FUNCTION DESCRIPTION
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memory. When the entire packet has been transferred to the Tx buffer, the SC92031 is instructed to move the
data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a
complete packet or is filled to the programmed threshold level, the SC92031 begins packet transmission.
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filtering of multicast packets according to its hash algorithms. When the amount of data in the Rx FIFO reaches
the level defined in the Receive Configuration Register, the SC92031 requests the PCI bus to begin transferring
the data to the Rx buffer in PCI bus master mode.
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transceiver and the network partner to automatically configure both to take maximum advantage of their abilities,
and both are setup accordingly. The Auto-Negotiation exchanges information with the network partner using the
Fast Link Pulses (FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in the burst
pulses to advertise all remote partner’ s capabilities which are determined by PHY register 4. According to this
information they find out their highest common capability by following the priority sequence as below:
Negotiation function will process. Otherwise, the Auto-Negotiation will not occur. When the Auto-Negotiation is
disabled, then the Network Speed and Duplex Mode are selected by programming PHY register 0.
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The MLT-3 encoder converts the NRZI data into a three level MLT-3 code required by IEEE 802.3u. MLT-3
coding uses three levels and converts 1's to transitions between the three levels, and converts 0's to no
transitions or changes in level. The purpose of the waveform generator is to shape the transmit output pulse. The
waveform generator eliminates the need for any external filters on the TP transmit output. The line driver
converts the shaped and smoothed wave-form to a current output that can drive 100 meters of category 5
unshielded twisted pair cable or 150 Ohm shielded twisted pair cable.
transmitter still consists of a waveform generator and line driver.
Ø
extracts the recovered clock that will be used to re-time the data stream and set the data boundaries.
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The host CPU initiates a transmission by storing an entire packet of data in one of the descriptors in the main
The incoming packet is placed in the SC92031's Rx FIFO. Concurrently, the SC92031 performs address
The Auto-Negotiation function is designed to provide the means to exchange information between the
During power-up or reset, if Auto-Negotiation is found enabled then FLPs will be transmitted and the Auto-
The transmitter operation in 100 Mbps mode consists of a MLT-3 encoder, waveform generator and line driver.
The transmitter operation in 10 Mbps mode is much different than the 100 Mbps transmitter. Even so, the
The receiver either in 10Mbps or 100Mbps mode is mainly a reverse procedure of transmitter
The Clock and Data Recovery (CDR) module uses a DPLL to lock onto the incoming data stream and to
Transmit operation
Receive Operation
Auto-negotiation
Transceiver
Clock and Data Recovery
1. 100BASE-TX full duplex
2. 100BASE-TX half duplex
3. 10BASE-T full duplex
4. 10BASE-T half duplex
REV:1.0
SC92031
Page 19 of 38
2004.08.03