lxt6155 Intel Corporation, lxt6155 Datasheet - Page 18

• Manufacturer Part Number: lxt6155
• Description: 155 Mbps Sdh/sonet/atm Transceiver
• Manufacturer: Intel Corporation

18
LXT6155 — 155 Mbps SDH/SONET/ATM Transceiver
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.2
2.3.2.1
2.3.2.2
Clocks
Parallel Mode
The LXT6155 accepts TPICLK synchronized with transmit input parallel data TPID<7:0>. The
data is serialized and transmitted at TTIP0/TRING0 or TTIP1/TRING1 depending on which line
encoding mode is selected. The LXT6155 in turn produces the receive output parallel clock
RPOCLK, that is recovered from incoming line data RTIP/RRING, and is synchronized with
receive output parallel data RPOD<7:0>.
Transmit Parallel Input Clock (TPICLK)
TPICLK is the transmit parallel input clock provided by the systems interface. This clock must be
nominally 19.44 MHz, synchronized with parallel input data TPID<7:0>. This clock is then
internally multiplied by 8 to produce a serial clock, used for parallel-to-serial conversion, line
drivers, and pulse reshaping. In HW mode (HWSEL = Low), TPID data is sampled on the falling
edge of TPICLK. In SW mode (HWSEL = High), the clock polarity can be inverted (Reg #0, bit
#3).
Receive Parallel Output Clock (RPOCLK)
RPOCLK is the parallel output clock that is recovered from the line input data RTIP/RRING. This
clock is at 19.44 MHz, synchronized with parallel output data RP0D<7:0>. In HW mode (HWSEL
= Low), the RPOCLK clock rising edge is at the center of eye opening of RPOD<7:0> as shown in
Figure 21. In SW mode (HWSEL = High), the clock polarity can be inverted (Reg #0, bit #2).
Under LOS (LOS=High) or Rx PLL loss of lock (LOCK=Low) conditions RPOCLK is switched to
the reference selected by the CIS control in HW mode, or Reg #0 bit #5 in SW mode. Also, the
parallel output is forced to all zeros. This feature can be disabled in SW mode (HWSEL = High)
via register #10, bit #7.
Serial Mode
At the transmit systems interface, the LXT6155 accepts the transmit input clock TSICLKP/
TSICLKN that is synchronized to incoming serial differential data TPOS/TNEG. At the line
interface, the LXT6155 accepts RTIP/RRING data and produces the clocks RSOCLKP/
RSOCLKN synchronized to receive output data RPOS/RNEG. RSOCLKP/RSOCLKN clock edges
are at the center of RPOS/RNEG.
Transmit Serial Input Clock (TSICLKP/TSICLKN)
TSICLKP/TSICLKN is the serial input clock from the overhead terminator. This 155.52 MHz
clock is rising edge centered with input serial data on TPOS and TNEG. These clock pins should be
left open when the LXT6155 operates in parallel mode.
Receive Serial Output Clock (RSOCLKP/RSOCLKN)
RSOCLKP/RSOCLKN is the serial clock recovered from the line input data on RTIP/RRING. This
155.52 MHz clock is falling edge centered with receive serial output data on RPOS/RNEG. These
clock pins should be left open when the LXT6155 operates in parallel mode. Under LOS
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