lxt6155 Intel Corporation, lxt6155 Datasheet - Page 9

• Manufacturer Part Number: lxt6155
• Description: 155 Mbps Sdh/sonet/atm Transceiver
• Manufacturer: Intel Corporation

Datasheet
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; AI/O = Analog Input/Output; S=Supply.
2. TTL = Transistor-to-Transistor Logic (5V tolerant); LVPECL = Low-Voltage positive ECL.
Pin #
10
12
13
14
15
11
1
2
3
4
5
6
7
8
9
Table 1.
CS/MODE
SDO/RIFE
XTALOUT
TSICLKN
SCLK/SP
TSICLKP
Symbol
TDGND
SDI/CIS
XTALIN
TAGND
TDVCC
TAVCC
TXISH
TPOS
TNEG
LXT6155 Pin Descriptions
AI/O
AI/O
DI/O
I/O
DI
DI
DI
DI
DI
S
S
S
S
1
LVPECL
LVPECL
Type
TTL
TTL
TTL
TTL
2
Crystal Input/Output. These pins are connected to an external 19.44
MHz crystal. Alternately, a stable external clock signal may be connected
to XTALIN with XTALOUT left open. XTALIN should be connected to
TAGND and XTALOUT should be left open if the transmit input clock is
used as a clock reference
Transmit Analog Ground.
Transmit PLL Loop Filter Pin. Connecting a capacitor to TAGND from
this pin controls the Tx PLL transfer function. This pin requires a 68nF
cap to TAGND.
Transmit Analog Power Supply.
Transmit Digital Power Supply.
Transmit Serial Input Clock, positive and negative. Differential
Transmit clocks at 155.52 MHz. These pins are disabled when parallel
mode is selected.
Transmit Serial Input Data, positive and negative. Differential input
data from an overhead terminator at 155.52 Mbps, clocked in by TSICLK.
These pins are disabled when parallel mode is selected.
Transmit Digital Ground.
Chip Select Input, software mode (HWSEL = High). Register
transactions through the P interface are initiated by the falling edge of
this signal.
Line Interface Mode, hardware mode (HWSEL = Low). Sets line
interface mode to LVPECL (MODE = Low) or CMI (MODE = High).
Serial Clock Input, software mode (HWSEL = High). Serial
Microprocessor uses this pin to clock in/out data. SCLK can be from 0 to
4.096 MHz.
Serial/Parallel Select, hardware mode (HWSEL = Low). When
SP = Low, serial systems interface is used. When SP = High, 8 bit
parallel system interface is used.
Serial Input Data, software mode (HWSEL = High). The serial data is
applied to this pin when the LXT6155 operates in software mode. SDI is
sampled on the rising edge of SCLK.
Clock Input Select, hardware mode (HWSEL = Low). CIS sets the
reference clock for centering the Rx PLL. If CIS = Low, then the LXT6155
uses the transmit input clock as the reference. If CIS = High, then the
LXT6155 uses the crystal clock input (XTALIN) as the reference.
Serial Output Data, software mode (HWSEL = High). The serial data
from the on-chip register is output on this pin in software mode. Data
output is valid on the rising edge of SCLK. This pin goes to a high
impedance state when the serial port is being written to or when CS is
High.
Receive Input Frame Enabler, hardware mode (HWSEL = Low). The
frame detection option is available only in parallel mode. If RIFE = Low,
then the LXT6155 disables the frame detection, and byte alignment. If
RIFE = High, then the LXT6155 enables the frame detection, and outputs
RPOD bytes aligned to the SONET/SDH framer. This feature, if used,
must be enabled prior to applying data to Rtip/Rring.
155 Mbps SDH/SONET/ATM Transceiver — LXT6155
Description
9