lxt6155 Intel Corporation, lxt6155 Datasheet - Page 31

• Manufacturer Part Number: lxt6155
• Description: 155 Mbps Sdh/sonet/atm Transceiver
• Manufacturer: Intel Corporation

Datasheet
1. SONET compliant LOS de-assertion refers to Bellcore GR-253, pages 6-16 (section 6.2.1.1.1), recommendation R6-54, LOS alarm is de-asserted
Bit
5:4
Bit
6:3
2:1
Bit
7:4
3:0
3
2
1
0
7
0
(cleared) when two valid frame headers have been received with no LOS events in the interval.
Table 20. Rx Digital 1, Register #12 (Address A<3:0>=1100) (Continued)
Figure 15. Rx Digital 2, Register #13 (Address A<3:0>=11001)
Table 21. Status Control, Register #14 (Address A<3:0>=1110)
Default
Default
Default
0.0.0.0
0.0.0.0
0.0.0.0
1.1
1.0
0
0
0
1
1
1
.
.
los_tran_deassert
los_tran_assert
rx_dig_reset
Mnemonic
Mnemonic
Mnemonic
frame_ena
stat_cont
los_ena
cnffp
-
LOS disable controls (amplitude LOS & digital LOS):
0 = disable
1 = enable
Byte align enable: If used, this feature must be enabled during system
configuration prior to applying data to the receiver. If this is not possible see
application note AN141 for further details.
0 = byte align disabled
1 = byte align enabled
Not for customer use
Not for customer use
Not for customer use
Rx digital circuitry reset. This can be used to minimize power comsumption when
the device is disabled but not powered down. It must be enabled when the device
is active
0 = reset
1 = normal operation
Frame pulse position. Refer to figure 5 for usage.
D-LOS transition density count for assertion:
00 = 128
01 = 512
10 = 3112
11 = 4096
A-LOS assertion integration period:
00 = 2048 bits
01 = 512 bits
10 = 128 bits
11 = 32 bits
D-LOS transition density count for de-assertion:
0 = 4/32
1 = SONET compliant
A-LOS de-assertion integration period:
0 = 0 bits
1 = 128 bits
Unused
Status register (register #15) mux control (indirect addressing to increase read
space)
155 Mbps SDH/SONET/ATM Transceiver — LXT6155
1
Description
Description
Description
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