ADMC401-PB Analog Devices, ADMC401-PB Datasheet
ADMC401-PB
Related parts for ADMC401-PB
ADMC401-PB Summary of contents
Page 1
... PM DM WATCH- DOG RAM RAM TIMER SERIAL PORTS 2 CHANNEL INTERVAL AUXILIARY SPORT 0 SPORT 1 TIMER PWM Single-Chip, DSP-Based ADMC401 PWMTRIP (Continued on Page 14) MOTOR CONTROL PERIPHERALS POWER- EVENT INTERRUPT ENCODER ON CAPTURE CONTROLLER INTERFACE RESET UNIT PRECISION 16-BIT 8 CHANNEL VOLTAGE PWM 12-BIT ADC ...
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... Output pins: AH, AL, BH, BL, CH and CL. 6 Although specified for TTL outputs, all ADMC401 outputs are CMOS-compatible and will drive Input only pins RESET, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE, BR and PWD. Input pins with internal pull-down PIO0–PIO11 and PWMTRIP. ...
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... AMB = 2.0 V, unless otherwise noted) REF Test Conditions SENSE = REFCOM SENSE = REFCOM 1.0 mA Load Current MAX = – +85 C, CLKIN = 13 MHz, unless otherwise noted) AMB Test Conditions ADMC401 = – +85 C, CLKIN = 13 MHz, AMB Typ Max Unit –76 –70 dB –89 – ...
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... Range ADMC401BST –40°C to +85°C ADMC401-ADVEVALKIT ADMC401-PB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC401 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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... Parameter Clock Signals t is defined as 0.5t The ADMC401 uses an input clock CK CKI. with a frequency equal to half the instruction rate MHz clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor cycle (equivalent to 26 MHz). t values within the range of CK 0.5t period should be substituted for all relevant timing CKI parameters to obtain specification value ...
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... ADMC401 Parameter Interrupts and Flags Timing Requirements: IRQx or FI Setup before CLKOUT Low t IFS IRQx or FI Hold after CLKOUT High t IFH Switching Characteristics: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay from CLKOUT Low FOD NOTES 1 If IRQx and FI inputs meet t and t setup/hold requirements, they will be recognized during the current clock cycle ...
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... BGH is asserted when the bus is granted and the processor requires control of the bus to continue. CLKOUT BR CLKOUT PMS, DMS BMS BGH Min 1 0.25t 1 0.25t 0 0 0.25t SDB t SDBH ADMC401 Max + 0.25t + 10 CK – SEC SEH Unit ...
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... ADMC401 Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, PMS, DMS, BMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, PMS, DMS, BMS Setup before RD Low t ASR A0–A13, PMS, DMS, BMS Hold after RD Deasserted ...
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... CK 0 0.25t – 0.25t – 0.25t – 0.75t – 0.25t – 0.5t – WRA t t ASW CWR WDE ADMC401 Max Unit 0.25t + WWR t DDR ...
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... ADMC401 Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV t TFS/RFS ...
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... SIGNAL DD (MEASURED) OUTPUT f × 26 MHz = 52.00 mW (MEASURED) × 13 MHz = 29.25 mW × 13 MHz = 3.25 mW × 26 MHz = 6.50 mW 91. mW. INT and t , MEASURED DECAY , and the cur DECAY ADMC401 3.0V INPUT 1.5V 0.0V 2.0V 1.5V OUTPUT 0. the interval from when ENA t MEASURED t V DIS OH V (MEASURED) – 0.5V 2. (MEASURED) +0.5V 1. DECAY ...
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... ADMC401 Pin Pin Pin No. Name No VDD GND PWD PWDACK BMODE 54 19 MMAP 55 20 VDD 56 21 GND 57 PWMSR 22 58 ...
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... DMS 136 RD 137 GND 138 BG 139 WR 140 A13 141 A12 142 PIN 1 A11 143 IDENTIFIER A10 144 PIN CONFIGURATION ADMC401 TOP VIEW (Not to Scale CONNECT ADMC401 72 D11 71 VDD 70 D12 69 D13 68 D14 67 D15 66 D16 65 D17 64 D18 63 GND 62 D19 61 D20 60 D21 ...
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... DSP core with a complete set of motor control peripherals that permits fast motor control in a highly integrated environment. The DSP core of the ADMC401 is the ADSP-2171 which is completely code compatible with the ADSP-21xx DSP family (as well as other members of the integrated motor controllers of the ADMC3xx family) and combines three computational units, data address generators and a program sequencer ...
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... R BUS ARCHITECTURE OVERVIEW Figure functional block diagram of the DSP core of the ADMC401. The DSP core is based on the fixed-point ADSP- 2171 core that is a member of the fixed-point ADSP-21xx family of general purpose DSPs from Analog Devices Inc. The ADSP-2171 flexible architecture and comprehensive in- struction set allow the processor to perform multiple operations in parallel ...
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... Data Memory Data (DMD) Bus. • Result (R) Bus. Program memory can store both instructions and data, permit- ting the ADMC401 to fetch two operands in a single cycle, one from internal program memory and one from internal data memory. The ADMC401 can fetch an operand from on-chip program memory and the next instruction in the same cycle ...
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... The ROMENABLE bit is initialized to zero after reset unless MMAP and BMODE = 1. When MMAP = BMODE = 0, the ADMC401 provides 2K × 24 bits of internal program memory RAM starting at address 0x0000 that is booted from a byte-wide interface on the address and data buses ...
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... The structure of the System Control Register is shown at the end of the data sheet. The data memory map of the ADMC401 is shown in Figure 13. The internal data memory RAM of the ADMC401 is arranged as a single 1K × 16-bit block starting at address 0x3800. In addition, there are two 1K blocks of reserved data memory space ...
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... If an external clock source is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is con- nected to the CLKIN pin of the ADMC401. In this mode, with an external clock signal, the XTAL pin must be left unconnected. Because the ADMC401 includes an on-chip oscillator circuit, an external crystal may be used instead of a clock source ...
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... The maximum baud rate that the ADMC401 will lock onto is 300 kb/s for a 26 MHz CLKOUT. The second byte of information received is the header byte that uniquely identifies to the monitor which type of interface it is connected to ...
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... The mode in which BMODE = 1 and MMAP = 0 is not allowed on the ADMC401 and is an illegal state. The operation of the ADMC401 is neither guaranteed nor defined with BMODE = 1 and MMAP = 0. ...
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... Unlike the standard ADSP- 21xx products, the XTALDIS bit of the Power-Down Register has no effect on the ADMC401 so that it is not possible to avoid the power drain caused by the XTAL pin toggling. When the processor comes out of power-down by either the PWD or RESET ...
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... The OTR bit for the ADCXTRA register is stored in the ADCSTAT register. The ADC may use either an internally generated 2.0 V precision reference voltage or an externally supplied reference voltage level at the V connection of the SENSE pin. ADMC401 pin. The operating mode is selected by the REF ...
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... VIN7 inputs are unipolar so that when operating from the internal 2.0 V reference, these signals can range from The recommended single-ended input configuration for a single analog input channel of the ADMC401 is shown in Fig- ure 18. The input to the A/D converter must be driven by an operational amplifier with sufficient drive strength so that the A/D performance is not degraded ...
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... The internal control logic subsequently multiplexes these two signals into the A/D core of the ADMC401. The conversion of each signal requires 3 1/2 ADC clock cycles. Following the hold operation, the VIN0 input is applied to the first stage of the pipeline during the next ADC clock cycle ...
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... The SENSE pin is used to select between internal and external references. The actual reference voltages used by the internal ADC circuitry of the ADMC401 appear on the CAPT and CAPB pins. For correct operation of the internal voltage reference generation circuitry, either with internal or external reference neces- sary to add a capacitor network between these pins, as shown in Figure 20 µ ...
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... The configuration and structure of the ADC registers is de- scribed at the end of this data sheet. THE PWM CONTROLLER OVERVIEW The PWM generator block of the ADMC401 is a flexible, pro- grammable, three-phase PWM waveform generator that can be programmed to generate the required switching patterns to drive pin and the ...
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... PWM shutdown pin, PWMTRIP, that, when brought LO, instantaneously places all six PWM outputs in the OFF state (as determined by the state of the PWMPOL pin). In addition, each of the PIO lines of the ADMC401 (PIO0 to PIO11) can be configured to act as an additional PWM shut- down. By setting the appropriate bit in the PIOPWM register, the corresponding PIO line acts as an asynchronous PWM shut- down source in a manner identical to the PWMTRIP pin ...
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... CLKOUT rate of 26 MHz. Obviously, the dead time can be programmed to be zero by writing 0 to the PWMDT register. PWM Operating Mode, MODECTRL and SYSSTAT Registers The PWM controller of the ADMC401 can operate in two distinct modes; single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 6 of the MODECTRL register ...
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... ADMC401 cycle of the signals on CH and CL. The duty cycle registers are programmed in integer counts of the fundamental time unit and define the desired on-time of the high side PWM signal CK produced by the three-phase timing unit over half the PWM pe- riod. The switching signals produced by the three-phase timing unit are also adjusted to incorporate the programmed dead time value in the PWMDT register ...
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... PWM unit is transitioning from the first half cycle to the second half cycle or vice versa. These transitions are detected automati- cally by the ADMC401 and, if appropriate, the dead time is inserted. The insertion of the additional dead time into one of the PWM ...
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... ADMC401 signals, setting Bit 7 enables crossover on the BH/BL pair of PWM signals and setting Bit 6 enables crossover on the CH/CL pair of PWM signals. If crossover mode is enabled for any pair of PWM signals, the high side PWM signal from the timing unit (AH say) is diverted to the associated low side output of the Output Control Unit so that the signal will ultimately appear at the AL pin ...
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... PWM will be disabled. The state of the PWMTRIP pin can be read from Bit 0 of the SYSSTAT register. The 12 PIO lines of the ADMC401 can also be configured to operate as PWM shutdown pins using the PIOPWM register. The 12-bit PIOPWM has a control bit for each PIO line (Bit 0 controls PIO0, etc ...
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... ADMC401 Table V. Fundamental Characteristics of PWM Generation Unit of ADMC401 (CLKOUT = 26 MHz) Parameter Counter Resolution Edge Resolution T Programmable Dead Time D Dead Time Increments T Programmable Minimum Pulsewidth MIN Minimum Pulsewidth Increments f PWM Switching Frequency PWM f PWM Switching Frequency PWM T PWMSYNC Pulsewidth PWMSYNC PWMSYNC Pulsewidth Increments ...
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... Four status bits in the EIUSTAT register provide the state of the four EIU inputs, EIA, EIB, EIZ and EIS. The encoder interface unit of the ADMC401 contains a 16-bit loop timer that behaves in a manner similar to the program- mable interval timer of the DSP core. The loop timer consist of a timer register, period register and scale register so that it can be programmed to timeout and reload at appropriate intervals ...
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... Therefore, if the EIA signal led the EIB signal at the pins of the ADMC401, the A input to the quadrature counter will now lag the B input. This will be recog- nized as rotation in the reverse direction and the counter will be decremented on each quadrature pulse. Following a reset, the REV bit is cleared ...
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... ENCODER EVENT TIMER Introduction and Overview The encoder event timer block forms an integral part of the EIU of the ADMC401, as shown in Figure 28. The EET accurately times the duration between encoder events. The information provided by the EET may be used to make allowances for the ADMC401 ...
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... ADMC401 asynchronous timing of encoder and DSP-reading events result, more accurate computations of the position and velocity of the motor shaft may be performed. The EET consists of a 16-bit encoder event timer, an encoder pulse decimator and a clock divider. The EET clock frequency is selected by the 16-bit read/write EETDIV clock divide register, whose value divides the CLKOUT frequency ...
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... Table VI. Fundamental Characteristics of Encoder Interface Unit of ADMC401 (At 26 MHz) Parameter f Encoder Input (EIA, EIB) Rate ENC f Quadrature Rate QUAD Encoder Loop Timer Timeout Rate T Minimum Encoder Pulsewidth MINENC EIU/EET Registers The structure and functionality of the EIU and EET registers are illustrated at the end of the data sheet. The characteristics of the EIU block at 26 MHz are given in Table VI ...
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... PIO REGISTERS The configuration of all registers associated with the PIO system of the ADMC401 are shown at the end of the data sheet. Each of the registers has a bit directly associated with one of the PIO lines. For example, Bit 0 of all registers affects only the PIO0 line of the ADMC401 ...
Page 41
... PWM out- put signals can be used as simple single-bit digital-to-analog converters. The auxiliary PWM system of the ADMC401 can operate in two different modes, independent mode or offset mode. The oper- ating mode of the auxiliary PWM system is controlled by Bit 8 of the MODECTRL register ...
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... The watchdog circuit is not reset by a software controlled Peripheral Reset. PROGRAMMABLE INTERRUPT CONTROLLER OVERVIEW The ADMC401 uses the IRQ2 pin of the DSP core to generate a peripheral interrupt. There are multiple sources of peripheral interrupts, e.g., the ADC block, PIO block, EIU block, ETU block and PWM block. A Programmable Interrupt Controller (PIC) is used to avoid a software latency in determining the source of the interrupt ...
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... UART and SPORT mode of SPORT1. Setting the UARTEN bit connects DR1A to the RFS1 input which allows SPORT1 to be used as a UART port. Additionally, the internal FL1 flag of the DSP core is connected to the RFS1/SROM pin of the ADMC401 used as a reset for the external serial ADMC401 DT1 DR1A ...
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... SYSSTAT REGISTER The SYSSTAT register provides various status information of the ADMC401, such as the state of the PWMTRIP pin, the state of the watchdog flag, the state of the PWMPOL pin and phase of the PWM Bit 0 indicates the state of the PWMTRIP pin such that the bit is set if PWMTRIP is HI and cleared if the pin is LO ...
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... ADCSTAT 0x203A 0x203B ADCXTRA 0x203C ADCOTR 0x203D–0x203F 0x2040 PIOLEVEL 0x2041 PIOMODE 0x2042 PIOPWM 0x2043 0x2044 PIODIR 0x2045 PIODATA Table VIII. Peripheral Register Map of the ADMC401 Type Bits Reset Value R/W [ 0x0000 R 0x0000 R 0x0000 R 0x000 R/W [ 0x0000 R/W [15 ...
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... R/W [ 0x0000 R 0x0 R 0x27 R/W [0] 0x0 R 0x00 R/W [ 0x0000 R [ 0x0000 R [ 0x0000 R [0] 0x0 Table IX. DSP Core Register Map of the ADMC401 Type Bits R/W [ R/W [ R/W [ R R/W [ R/W [ R/W [ R/W [ R/W [ R/W [ R/W [ R/W [ R/W [15 ...
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... ADC MODE ADCSTAT ( ADCXTRA OTR ADMC401 DM (0x2030) DM (0x2031) DM (0x2032 (0x2033) DM (0x2034 (0x2035) DM (0x2036) DM (0x2037) DM (0x203B (0x203C) ADC0 OTR ADC1 OTR RANGE 1 = OUT OF RANGE ADC2 OTR ADC3 OTR ...
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... ADMC401 LOW-SIDE CHOPPING 1 = ENABLE 0 = DISABLE HIGH-SIDE CHOPPING AH/AL CROSSOVER 1 = ENABLE BH/BL CROSSOVER 0 = DISABLE CH/CL CROSSOVER Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... EIUCTRL (R/ ADMC401 (0x2020) DM (0x2021) DM (0x2024) DM (0x2026) DM (0x2027 (0x2025 (0x2022 ERROR EIU COUNT ERROR ERROR EIU COUNT 0 = DOWN DIRECTION 1 = NOT INITIALIZED EIU ...
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... ADMC401 Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... PIOINTEN (R/ PIOFLAG ( ADMC401 (0x2040 (0x2041 (0x2042) ...
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... ADMC401 ETU1 MODE 0 = SINGLE SHOT 1 = FREE-RUNNING ETU1 INTERRUPT 0 = NEXT EVENT EVENT B ETU1 EVENT FALLING EDGE 1 = RISING EDGE ETU1 EVENT FALLING EDGE 1 = RISING EDGE ...
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... T OFFSET = 2 PICMASK (R/ PIO3 INTERRUPT PIO2 INTERRUPT PIO1 INTERRUPT PIO0 INTERRUPT ETU INTERRUPT ADMC401 (0x2010) AUXCH0 (0x2011 AUXCH1 ...
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... ADMC401 INDEPENDENT AUXILIARY 0 = OFFSET PWM MODE 1 = DOUBLE UPDATE 0 = SINGLE UPDATE SECOND HALF CYCLE 0 = FIRST HALF CYCLE Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... SPORT0 RECEIVE IFC (R/ ADMC401 DSP REGISTER 1 = ENABLE DISABLE TIMER IRQ0 or SPORT1 RECEIVE IRQ1 or SPORT1 TRANSMIT SOFTWARE 0 SOFTWARE DSP REGISTER 0 0 ...
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... ADMC401 ASTAT (R/ SPORT0 ENABLE 1 = ENABLE DISABLED SPORT1 ENABLE 1 = ENABLE DISABLED SPORT1 CONFIGURE 1 = SERIAL PORT 0 = FI, FO, IRQ0, IRQ1, SCLK Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... DM (0x3FFA (0x3FF9) SPORT0_CTRL_REG (R/ ADMC401 (0x3FFE) DWAIT0 SPORT0_TX_WORDS1 (R/ CHANNEL ENABLE 0 = CHANNEL IGNORED SPORT0_TX_WORDS0 (R/ ...
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... ADMC401 CLKODIS CLKOUT DISABLE CONTROL BIT BIASRND MAC BIASED ROUNDING CONTROL BIT TIREG TRANSMIT AUTOBUFFER I REGISTER TMREG TRANSMIT AUTOBUFFER MREGISTER Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown ...
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... SPORT1_CTRL_REG (R/ ADMC401 (0x3FF1 (0x3FF0 (0x3FEF RBUF RECEIVE AUTOBUFFER ENABLE TBUF TRANSMIT AUTOBUFFER ENABLE RMREG RECEIVE M REGISTER RIREG RECEIVE I REGISTER TMREG ...
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... ADMC401 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.003 (0.08) 0.006 (0.15) 0.002 (0.05) Only dimensions in mm are accurate. The inch equivalents are approximations rounded to three decimal places. Only the mm values are recommended for use in PCB layout. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 144-Lead Plastic Thin Quad Flatpack (LQFP) ST-144 0 ...