M29W800AB STMICROELECTRONICS [STMicroelectronics], M29W800AB Datasheet
M29W800AB
Available stocks
Related parts for M29W800AB
M29W800AB Summary of contents
Page 1
... YEARS DATA RETENTION – Defectivity below 1ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M29W800AT: D7h – Bottom Device Code, M29W800AB: 5Bh March 2000 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory TSOP48 ( 20mm Figure 1 ...
Page 2
... M29W800AT, M29W800AB Figure 2. TSOP Connections A15 1 48 A14 A13 A12 A11 A10 M29W800T M29W800B A18 A17 AI02179 Table 1. Signal Names A0-A18 Address Inputs DQ0-DQ7 Data Input/Outputs, Command Inputs DQ8-DQ14 Data Input/Outputs DQ15A– ...
Page 3
... KWords and fifteen Main Blocks of 64 KBytes or 32 KWords. The M29W800AT has the Boot Block at the top of the memory address space and the M29W800AB locates the Boot Block starting at the bottom. The memory maps are showed in Figure 5. Each block can be erased separately, any combi- nation of blocks can be specified for multi-block erase or the entire chip may be erased ...
Page 4
... M29W800AT, M29W800AB Table 2. Absolute Maximum Ratings Symbol T Ambient Operating Temperature A T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or Output Voltage Supply Voltage CC (2) A9 Voltage V (A9 RP) Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device ...
Page 5
... M29W800AT, M29W800AB Table 4. Bottom Boot Block Addresses, M29W800AB Size Address Range # (x16) (Kbytes F0000h-FFFFFh 17 64 E0000h-EFFFFh 16 64 D0000h-DFFFFh 15 64 C0000h-CFFFFh 14 64 B0000h-BFFFFh 13 ...
Page 6
... M29W800AT, M29W800AB SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs for the memory array are latched during a write op- eration on the falling edge at Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A18, in Byte-wide organisa- tion DQ15A– ...
Page 7
... The manufacturer’s code for STMicro- electronics is 20h, the device code is D7h for the M29W800AT (Top Boot) and 5Bh for the M29W800AB (Bottom Boot). These codes allow programming equipment or applications to auto- matically match their interface to the characteris- tics of the M29W800A. The Electronic Signature is ...
Page 8
... M29W800AT, M29W800AB (1) Table 5. User Bus Operations Operation Read Word Read Byte Write Word Write Byte Output Disable Stan- Reset Block Pulse V IL ...
Page 9
... Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from ’0’ to ’1’ at the start of the Erase Suspend. In order to M29W800AT, M29W800AB monitor DQ7 in the Erase Suspend mode an ad- dress within a block being erased must be provid- ed. For a Read Operation in Erase Suspend mode, DQ7 will output ’ ...
Page 10
... M29W800AT, M29W800AB (1) Table 9. Instructions Mne. Instr. Cyc. (3,7) Addr. 1+ Data Read/Reset (2,4) RD Byte Memory Array (3,7) Addr. 3+ Word Data Byte (3,7) Addr. (4) Auto Select 3+ Word AS Data Byte (3,7) Addr. Word PG Program 4 Data Byte (3,7) Addr. BE Block Erase 6 Word Data Byte (3,7) Addr. CE Chip Erase 6 Word Data (3,7) Addr. Erase ...
Page 11
... Reserved 0 Reserved Note: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. M29W800AT, M29W800AB Definition Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for program or Erase Success. Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going ...
Page 12
... M29W800AT, M29W800AB Table 11. Polling and Toggle Bits Mode DQ7 DQ6 Program DQ7 Toggle Erase 0 Toggle Erase Suspend Read (in Erase Suspend 1 1 block) Erase Suspend Read (outside Erase Suspend DQ7 DQ6 block) Erase Suspend Program DQ7 Toggle Note: 1. Toggle if the address is within a block being erased. ...
Page 13
... V A9 Voltage (Electronic Signature Current (Electronic Signature) ID Supply Voltage (Erase and (1) V LKO Program lock-out) Note: 1. Sampled only, not 100% tested. M29W800AT, M29W800AB Figure 6. AC Testing Load Circuit 10ns 1.5V DEVICE UNDER TEST 1.5V AI01417 C L includes JIG capacitance Test Condition ...
Page 14
... RP Pulse Width PLPX RP Note: 1. Sampled only, not 100% tested may be delayed ELQV GLQV considered only if the Reset pulse is given while the memory is in Erase or Program mode. 14/33 M29W800AT / M29W800AB 80 Test V = 3.0V to 3.6V Conditio 30pF Min Max IL, ...
Page 15
... RP Pulse Width PLPX RP Note: 1. Sampled only, not 100% tested may be delayed ELQV GLQV considered only if the Reset pulse is given while the memory is in Erase or Program mode. M29W800AT, M29W800AB M29W800AT / M29W800AB 100 Test V = 2.7V to 3.6V Conditio 30pF Min Max ...
Page 16
... M29W800AT, M29W800AB Figure 7. Read Mode AC Waveforms 16/33 ...
Page 17
... Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Cod- ed cycles. The erase will start after the erase tim- eout period (see Erase Timer Bit DQ3 description). M29W800AT, M29W800AB M29W800AT / M29W800AB 3. 30pF ...
Page 18
... In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C. Chip Erase (CE) Instruction. This uses six write cycles. The Erase Set-up command 80h is written to address AAAh in the Byte-wide configuration or the address 555h in the Word- 18/33 M29W800AT / M29W800AB 100 V = 2. 30pF Min Max ...
Page 19
... P/E.C. is suspended. The Toggle bits will stop toggling between 0.1 s and 15 s after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is M29W800AT, M29W800AB tAVAV VALID tWLAX tWHEH tWHGL ...
Page 20
... The memory Command Interface is reset on pow Read Array. The device does not accept commands on the first rising edge both W and E are at V with during power-up Any write cycle initiation is blocked when V below V . LKO 20/33 M29W800AT / M29W800AB 3. 30pF Min Max ...
Page 21
... V High to Write Enable Low VCHWL VCS Write Enable Low to Chip Enable Low WLEL WS Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. M29W800AT, M29W800AB M29W800AT / M29W800AB 100 V = 2. 30pF Min Max 100 ...
Page 22
... M29W800AT, M29W800AB Figure 9. Write AC Waveforms, E Controlled A0-A18/ A–1 tAVEL W tWLEL G tGHEL E DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E. Figure 10. Read and Write AC Characteristics, RP Related 22/33 tAVAV VALID tELAX tEHWH ...
Page 23
... CL = 30pF Min Max Min Max 10 2400 10 2400 1 2400 10 2400 1 2400 10 2400 1 2400 10 2400 1.0 60 1.0 60 (1) M29W800AT / M29W800AB 100 120 V = 2. 2. 30pF CL = 30pF Min Max Min Max 10 2400 10 2400 1 2400 10 2400 1 2400 10 2400 1.0 60 1.0 60 ...
Page 24
... M29W800AT, M29W800AB Figure 11. Data Polling DQ7 AC Waveforms 24/33 ...
Page 25
... Byte/Word Program Program/Erase Cycles (per Block) Note: 1. Excluded the time required to execute bus cycles sequence for program operation. Figure 13. Data Toggle Flowchart DQ2, DQ5 & DQ6 NO READ DQ2, DQ6 PASS AI01369 M29W800AT / M29W800AB Typical after Min Typ 100k W/E Cycles ...
Page 26
... M29W800AT, M29W800AB Figure 14. Data Toggle DQ6, DQ2 AC Waveforms 26/33 ...
Page 27
... Unlock Cycle 1st Cyc. (1) AAh Read OTP Data until a new write cycle is initiated. (2) B8h BYTE Organisation (x8) BOTTOM BOOT BLOCK Security Memory Block WORD Organisation (x16) BOTTOM BOOT BLOCK Security Memory Block M29W800AT, M29W800AB 2nd Cyc. 0E0FFh 0E000h 0E01Fh 0E000h AI02746 27/33 ...
Page 28
... M29W800AT, M29W800AB Table 25. Ordering Information Scheme Example: Device Type M29 Operating Voltage W = 2.7 to 3.6V Device Function 800A = 8 Mbit (1Mb x8 or 512Kb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 100 = 100 ns 120 = 120 ns Package N = TSOP48 SO44 ZA = LFBGA48: 0 ...
Page 29
... Program, Erase Times and Erase Endurance Cycles change New document template Document type: from Preliminary Data to Data Sheet 02/09/00 Program, Erase Times and Endurance Cycles change (Table 23) LFBGA Package Mechanical Data change (Table 29) LFBGA Package Outline drawing change (Figure 18) 03/06/00 Program Erase Times change (Table 23) M29W800AT, M29W800AB Description 29/33 ...
Page 30
... M29W800AT, M29W800AB Table 27. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, Package Mechanical Data Symbol Typ 19.80 D1 18.30 E 11. Figure 16. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, Package Outline 1 N DIE TSOP-a Drawing is not to scale. 30/33 mm Min Max Typ 1 ...
Page 31
... Min Max Typ 2.42 2.62 0.22 0.23 2.25 2.35 0.50 0.10 0.25 28.30 13.40 – – 0.0500 16.10 – – 0.0315 – – 0. M29W800AT, M29W800AB inches Min Max 0.0953 0.1031 0.0087 0.0091 0.0886 0.0925 0.0197 0.0039 0.0098 1.1063 1.1142 0.5197 0.5276 – – 0.6260 0.6339 – – – – 44 0.0039 C L 31/33 ...
Page 32
... M29W800AT, M29W800AB Table 29. LFBGA48 - balls, 0.8 mm pitch, Package Mechanical Data Symbol Typ A A1 0.300 0.200 A2 0.750 b 0.300 D 9.000 8.800 D1 5.600 ddd e 0.800 E 6.000 5.800 E1 4.000 FD 1.700 FE 1.000 SD 0.400 SE 0.400 Figure 18. LFBGA48 - balls, 0.8 mm pitch, Bottom View Package Outline BALL ”A1” ...
Page 33
... All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . 2000 STMicroelectronics - All Rights Reserved http://w ww.st.com M29W800AT, M29W800AB 33/33 ...