M29W800AB STMICROELECTRONICS [STMicroelectronics], M29W800AB Datasheet - Page 17

• Manufacturer Part Number: M29W800AB
• Description: 8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 17. Write AC Characteristics, W Controlled
(T
Note: 1. Sampled only, not 100% tested.
Block Erase (BE) Instruction. This
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address AAAh
in the Byte-wide configuration or address 555h in
the Word-wide configuration on third cycle after
the two Coded cycles. The Block Erase Confirm
command 30h is similarly written on the sixth cycle
after another two Coded cycles. During the input of
the second command an address within the block
to be erased is given and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. The erase will start after the erase tim-
eout period (see Erase Timer Bit DQ3 description).
t
PHPHH
A
t
t
Symbol
WHRL
PHWL
t
t
t
t
t
t
t
t
t
t
= 0 to 70 C, –20 to 85 C or –40 to 85 C)
t
t
VCHEL
t
WHDX
WHEH
WHWL
WLWH
DVWH
GHWL
WHGL
WLAX
AVWL
ELWL
AVAV
PLPX
2. This timing is for Temporary Block Unprotection operation.
(1, 2)
(1)
(1)
t
t
t
t
t
t
BUSY
t
VIDR
WPH
t
t
t
t
RSP
t
VCS
t
t
OEH
t
Alt
WC
WP
AS
DS
CS
RP
DH
CH
AH
Address Valid to Next Address Valid
Address Valid to Write Enable Low
Input Valid to Write Enable High
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
RP Rise Time to V
RP High to Write Enable Low
RP Pulse Width
V
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Program Erase Valid to RB Delay
Write Enable High to Write Enable Low
Write Enable Low to Address Transition
Write Enable Low to Write Enable High
CC
High to Chip Enable Low
Parameter
ID
instruction
Thus, additional Erase Confirm commands for oth-
er blocks must be given within this delay. The input
of a new Erase Confirm command will restart the
timeout period. The status of the internal timer can
be monitored through the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.C. is erasing the Block(s). If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris-
ing edge of W or E output the status register status
bits.
V
CC
Min
500
500
80
35
50
30
45
35
0
0
0
4
0
0
0
CL = 30pF
= 3.0V to 3.6V
M29W800AT / M29W800AB
80
Max
90
M29W800AT, M29W800AB
V
CC
Min
500
500
90
45
50
30
45
35
0
0
0
4
0
0
0
CL = 30pF
= 3.0V to 3.6V
90
Max
90
Unit
17/33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s