M29W800AB STMICROELECTRONICS [STMicroelectronics], M29W800AB Datasheet - Page 9

no-image

M29W800AB

Manufacturer Part Number
M29W800AB
Description
8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M29W800AB
Manufacturer:
ST
0
Part Number:
M29W800AB-100N1
Manufacturer:
ST
Quantity:
2 000
Part Number:
M29W800AB-100N1
Manufacturer:
ST
Quantity:
3 590
Part Number:
M29W800AB-100N1
Manufacturer:
ST
0
Part Number:
M29W800AB-100N1E
Manufacturer:
ST
0
Part Number:
M29W800AB-120N1
Manufacturer:
ST
0
Part Number:
M29W800AB-120N1E
Manufacturer:
ST
0
Part Number:
M29W800AB-80N1
Manufacturer:
ST
Quantity:
20 000
Part Number:
M29W800AB-80NI
Manufacturer:
ST
Quantity:
430
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structions require from 1 to 6 cycles, the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirm the first command or
execute the command immediately. Command se-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security. In-
structions are initialised by two initial Coded cycles
which unlock the Command Interface. In addition,
for Erase, instruction confirmation is again preced-
ed by the two Coded cycles.
Status Register Bits
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand execution will automatically output these
five Status Register bits. The P/E.C. automatically
sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other
bits (DQ0, DQ1 and DQ4) are reserved for future
use and should be masked. See Tables 10 and 11.
Data Polling Bit (DQ7). When Programming op-
erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be per-
formed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to ’0’ for about 100 s, and then return to the
previous addressed memory data value. See Fig-
ure 13 for the Data Polling flowchart and Figure 12
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be provid-
ed. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
on a block being erased and the data value on oth-
er blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behavior as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6). When Programming or Eras-
ing operations are in progress, successive at-
tempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G,
or E when G is low. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last pro-
grammed or a ’1’ after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. If the blocks selected for
erasure are protected, DQ6 will toggle for about
100 s and then return back to Read. DQ6 will be
set to ’1’ if a Read operation is attempted on an
Erase Suspend block. When erase is suspended
DQ6 will toggle during programming operations in
a block different to the block in Erase Suspend. Ei-
ther E or G toggling will cause DQ6 to toggle. See
Figure 14 for Toggle Bit flowchart and Figure 15
for Toggle Bit waveforms.
Table 8. Commands
Hex Code
00h
10h
20h
30h
80h
90h
A0h
B0h
F0h
Invalid/Reserved
Chip Erase Confirm
Reserved
Block Erase Resume/Confirm
Set-up Erase
Read Electronic Signature/
Block Protection Status
Program
Erase Suspend
Read Array/Reset
M29W800AT, M29W800AB
Command
9/33

Related parts for M29W800AB