M29W800AB STMICROELECTRONICS [STMicroelectronics], M29W800AB Datasheet - Page 18

• Manufacturer Part Number: M29W800AB
• Description: 8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29W800AT, M29W800AB
Table 18. Write AC Characteristics, W Controlled
(T
Note: 1. Sampled only, not 100% tested.
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
and Read/Reset RD instructions. Data Polling bit
DQ7 returns ’0’ while the erasure is in progress
and ’1’ when it has completed. The Toggle bit DQ2
and DQ6 toggle during the erase operation. They
stop when erase is completed. After completion
the Status Register bit DQ5 returns ’1’ if there has
been an erase failure. In such a situation, the Tog-
gle bit DQ2 can be used to determine which block
is not correctly erased. In the case of erase failure,
a Read/Reset RD instruction is necessary in order
to reset the P/E.C.
Chip Erase (CE) Instruction. This
uses six write cycles. The Erase Set-up command
80h is written to address AAAh in the Byte-wide
configuration or the address 555h in the Word-
18/33
t
PHPHH
A
t
t
Symbol
WHRL
PHWL
t
t
t
t
t
t
t
t
t
t
= 0 to 70 C, –20 to 85 C or –40 to 85 C)
t
t
VCHEL
t
WHDX
WHEH
WHWL
WLWH
DVWH
GHWL
WHGL
WLAX
AVWL
ELWL
AVAV
PLPX
2. This timing is for Temporary Block Unprotection operation.
(1, 2)
(1)
(1)
t
t
t
t
t
t
BUSY
t
VIDR
WPH
t
t
t
t
RSP
t
VCS
t
t
OEH
t
Alt
WC
WP
AS
DS
CS
RP
DH
CH
AH
Address Valid to Next Address Valid
Address Valid to Write Enable Low
Input Valid to Write Enable High
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
RP Rise Time to V
RP High to Write Enable Low
RP Pulse Width
V
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Program Erase Valid to RB Delay
Write Enable High to Write Enable Low
Write Enable Low to Address Transition
Write Enable Low to Write Enable High
CC
High to Chip Enable Low
Parameter
ID
instruction
wide configuration on the third cycle after the two
Coded cycles. The Chip Erase Confirm command
10h is similarly written on the sixth cycle after an-
other two Coded cycles. If the second command
given is not an erase confirm or if the Coded cy-
cles are wrong, the instruction aborts and the de-
vice is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will
automatically do this before erasing it to FFh.
Read operations after the sixth rising edge of W or
E output the Status Register bits. During the exe-
cution of the erase by the P/E.C., Data Polling bit
DQ7 returns ’0’, then ’1’ on completion. The Toggle
bits DQ2 and DQ6 toggle during erase operation
and stop when erase is completed. After comple-
tion the Status Register bit DQ5 returns ’1’ if there
has been an Erase Failure.
V
CC
Min
100
500
500
45
50
30
45
35
0
0
0
4
0
0
0
CL = 30pF
= 2.7V to 3.6V
M29W800AT / M29W800AB
100
Max
90
V
CC
Min
120
500
500
50
50
30
50
50
0
0
0
4
0
0
0
CL = 30pF
= 2.7V to 3.6V
120
Max
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s