PCF8531U2D NXP [NXP Semiconductors], PCF8531U2D Datasheet - Page 21

• Manufacturer Part Number: PCF8531U2D
• Description: 34 x 128 pixel matrix driver Single-chip LCD controller and driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8531
Product data sheet
9.2.1 PD
9.2.2 V
9.2 Function set
9.3 Set Y address
9.4 Set X address
9.5 Set multiplex rate
9.6 Display control (D, E, and IM)
When PD = 1, the power-down mode of the LCD driver is active:
When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as
shown in
into the DDRAM as shown in
Y address is 5.
Bits Y2, Y1, and Y0 define the Y address vector of the display RAM (see
Table 6.
The X address points to the columns. The range of X is 0 to 127 (7Fh).
M[1:0] selects the multiplex rate (see
Table 7.
Bits D and E select the display mode (see
to icon mode.
Y2
0
0
0
0
1
1
Multiplex rate
1:17
1:26
1:34
•
•
•
•
•
•
All LCD outputs at V
Power-On Reset (POR) detection active, oscillator off
V
I
RAM contents not cleared; RAM data can be written
Register settings remain unchanged
2
LCD
C-bus is operational, commands can be executed
can be disconnected
Figure
Y address
Multiplex rates
All information provided in this document is subject to legal disclaimers.
10. When V = 1 the vertical addressing is selected. The data is written
Y1
0
0
1
1
0
0
Rev. 6 — 16 May 2011
SS
(display off)
Figure
M1
0
1
0
9. Icon data is written independently of V when
Table
Table
7).
Y0
0
1
0
1
0
1
13). Bit IM (see
M0
0
0
1
34 x 128 pixel matrix driver
Table
Bank
0
1
2
3
4
5 (icons)
12) sets the display
PCF8531
© NXP B.V. 2011. All rights reserved.
Table
6).
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