PCF8531U2D NXP [NXP Semiconductors], PCF8531U2D Datasheet - Page 30

• Manufacturer Part Number: PCF8531U2D
• Description: 34 x 128 pixel matrix driver Single-chip LCD controller and driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8531
Product data sheet
10.2 I
This driver does not support read. The PCF8531 is a slave receiver. Therefore, it only
responds when R/W = 0 in the slave address byte.
Before any data is transmitted on the I
first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8531.
The least significant bit of the slave address is set by connecting the input SA0 to either
logic 0 (V
The I
The sequence is initiated with a START condition (S) from the I
followed by the slave address. All slaves with the corresponding address acknowledge in
parallel, all others ignore the I
command words follow, which define the status of the addressed slaves. A command
word consists of a control byte, which defines Co and RS, plus a data byte (see
and
The last control byte is tagged with a cleared most significant bit, the continuation bit Co.
The control and data bytes are also acknowledged by all addressed slaves on the bus.
After the last control byte, depending on the RS bit setting, either a series of display data
bytes or command data bytes may follow. If the RS bit was set logic 1, these display bytes
are stored in the display RAM at the address specified by the data pointer.
The data pointer is automatically updated and the data is directed to the intended
PCF8531 device. If the RS bit of the last control byte was set logic 0, these command
bytes will be decoded and the setting of the device will be changed according to the
received commands. The acknowledgement after each byte is made only by the
addressed PCF8531. At the end of the transmission, the I
condition (P).
2
Fig 17. Acknowledge on the I
C-bus protocol
Table
2
C-bus protocol is shown in
by transmitter
data output
by receiver
data output
SS
SCL from
11).
) or logic 1 (V
master
All information provided in this document is subject to legal disclaimers.
condition
START
S
Rev. 6 — 16 May 2011
DD
).
2
2
C-bus transfer. After acknowledgement, one or more
C-bus
Figure
1
2
C-bus, the device that must respond is addressed
18.
2
2
not acknowledge
C-bus master issues a STOP
34 x 128 pixel matrix driver
acknowledge
2
8
C-bus master, and is
acknowledgement
clock pulse for
PCF8531
© NXP B.V. 2011. All rights reserved.
9
mbc602
Figure 19
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