PCF88332DA PHILIPS [NXP Semiconductors], PCF88332DA Datasheet - Page 63

• Manufacturer Part Number: PCF88332DA
• Description: STN RGB - 132 X 132 X 3 driver
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
7.2.2
The function of the arbiter is to handle the data flow. If a
write access is done on the RAM and a read access is
requested at the same time, then the arbiter will ensure
that there are no data collisions. Writing data to the RAM
has priority. Therefore no handshaking is done at the
interface side and the data can be applied to the interface
without having data read/write errors on the RAM.
7.2.3
The address counter sets the addresses of the display
data RAM for writing.
Data is written pixel wise into the RAM of the PCF8833.
The data for one pixel is collected (RGB 4 : 4 : 4 bit) before
it is written into the display data RAM. The RAM locations
are addressed by the address pointers. The address
ranges are X = 0 to X = 131 (83H) and Y = 0 to
Y = 131 (83H). Addresses outside of these ranges are not
allowed.
Before writing to the RAM a window must be defined into
which data will be written. The window is programmable
via the command registers xs and ys (designating the start
address) and xe and ye (designating the end address).
2003 Feb 14
STN RGB - 132
handbook, halfpage
R
WR
AM ACCESS ARBITER
131
0
ADDRESS COUNTER
0
V = 0; MX = 0 and MY = 0.
Fig.34 Sequence of writing data bytes into RAM showing function of V bit.
xs
X address
132
xe
3 driver
MGU943
131
ye
ys
handbook, halfpage
63
For example, if the whole display content is written, the
window will be defined by the following values: xs = 0 (0H),
ys = 0 (0H), xe = 131 (83H) and ys = 131 (83H).
In the vertical addressing mode (V = 1), the Y address
increments after each pixel. After the last Y address
(Y = ye), Y wraps around to ys and X increments to
address the next column. In horizontal addressing mode
(V = 0), the X address increments after each pixel. After
the last X address (X = xe), X wraps around to xs and
Y increments to address the next row. After the very last
address (X = xe and Y = ye) the address pointers wrap
around to address (X = xs and Y = ys).
For flexibility in handling a wide variety of display
architectures, the command ‘Memory Data Access
Control (MADCTL)’ (see Section 6.2.27) defines flags
MX and MY, which allows mirroring of the X and
Y addresses. All combinations of flags are allowed.
Figures 34, 35 and 36 show the possible combinations of
writing to the display RAM. When MX, MY and V is
changed, the data must be re-written to the display RAM.
7.2.4
The display address counter generates the addresses for
readout of the display data RAM.
131
0
0
D
ISPLAY ADDRESS COUNTER
V = 1; MX = 0 and MY = 0.
xs
X address
xe
Objective specification
MGU944
131
PCF8833
ye
ys