AD9874BST AD [Analog Devices], AD9874BST Datasheet - Page 17

• Manufacturer Part Number: AD9874BST
• Description: IF Digitizing Subsystem
• Manufacturer: AD [Analog Devices]

The AD9874 also provides the means for controlling the switching
characteristics of the digital output signals via the DS (drive
strength) field of the SSICRB. This feature is useful in limiting
switching transients and noise from the digital output that may
ultimately couple back into the analog signal path, potentially
degrading the AD9874’s sensitivity performance. Figures 3c and
3d show how the NF can vary as a function of the SSI setting for
an IF frequency of 109.65 MHz. The following two observations
can be made from these figures:
• The NF becomes more sensitive to the SSI output drive strength
• The NF is dependent on the number of bits within an SSI frame,
Table V lists the typical output rise/fall times as a function of
DS for a 10 pF load. Rise/fall times for other capacitor loads can
be determined by multiplying the typical values presented in
Table V by a scaling factor equal to the desired capacitive load
divided by 10 pF.
*Blackfin is a registered trademark of Analog Devices, Inc.
REV. 0
level at higher signal bandwidth settings.
becoming more sensitive to the SSI output drive strength level
as the number of bits is increased. As a result, one should select
the lowest possible SSI drive strength setting that still meets
the SSI timing requirements.
Figure 3c. NF vs. SSI Output Drive Strength
(VDDx = 3.0 V, f
Figure 3d. NF vs. SSI Output Drive Strength
(VDDx = 3.0 V, f
10.0
9.2
8.2
9.8
9.6
9.4
9.0
8.8
8.6
8.4
8.0
12
14
13
11
10
9
8
7
1
1
2
2
SSI OUTPUT DRIVE STRENGTH SETTING
SSI OUTPUT DRIVE STRENGTH SETTING
CLK
CLK
16-BIT I/O DATA
3
3
= 18 MSPS, BW = 75 kHz)
= 18 MSPS, BW = 10 kHz)
24-BIT I/O DATA
24-BIT I/O DATA
4
4
16-BIT I/O DATA
5
5
w/DVGA ENABLED
w/DVGA ENABLED
16-BIT I/O DATA
16-BIT I/O DATA
6
6
7
7
–17–
Table V. Typical Rise/Fall times (± 25 %) with a 10 pF
Capacitive Load for Each DS Setting
Synchronization
Applications, such as receiver diversity, employing more than
one AD9874 device may desire synchronization of the digital
output data. SYNCB can be used for this purpose and applied
upon system initialization. It is an active-low signal that clears
the clock counters in both the decimation filter and the SSI
port. The counters in the clock synthesizers are not reset, since
it is presumed that the CLK signals of multiple chips would be
connected together. SYNCB also clears the registers in the
decimation filter and resets the modulator. As a result, valid
data representative of the input signal will be available once the
digital filters have been flushed.
Figure 4a shows the timing relationship between SYNCB and the
SSI port’s CLKOUT and FS signals. SYNCB is an asynchronous
active-low signal that must remain low for at least half an input
clock period (i.e., 1/(2 × f
FS remains low upon SYNCB going low. CLKOUT will become
active within 1 to 2 output clock periods upon SYNCB returning
high. FS will reappear several output clock cycles later, depend-
ing on the digital filter’s decimation factor and the SSIORD
setting. To verify proper synchronization, the FS signals of the
multiple AD9874 devices should be monitored.
CLKOUT
INTERFACING TO DSPs
The AD9874 connects directly to an Analog Devices program-
mable digital signal processor (DSP). Figure 4b illustrates an
example with the Blackfin
The Blackfin DSP series is a family of 16-bit products optimized
for telecommunications applications with its dynamic power
management feature making it well suited for portable radio
products. The code compatible family members share the funda-
mental core attributes of high performance, low power consumption,
and the ease-of-use advantages of microcontroller instruction set.
SYNCB
FS
Figure 4a. SYNCB Timing
®
CLK
DS
0
1
2
3
4
5
6
7
series of ADSP-2153x processors.
) ). CLKOUT returns high while
typ (ns)
13.5
7.2
5.0
3.7
3.2
2.8
2.3
2.0
AD9874