AD9874BST AD [Analog Devices], AD9874BST Datasheet - Page 27

• Manufacturer Part Number: AD9874BST
• Description: IF Digitizing Subsystem
• Manufacturer: AD [Analog Devices]

VARIABLE GAIN AMPLIFIER OPERATION WITH
AUTOMATIC GAIN CONTROL
The AD9874 contains both a variable gain amplifier (VGA) and
a digital VGA (DVGA) along with all of the necessary signal estima-
tion and control circuitry to implement automatic gain control
(AGC), as shown in Figure 18. The AGC control circuitry provides
a high degree of programmability, allowing users to optimize the
AGC response as well as the AD9874’s dynamic range for a given
application. The VGA is programmable over a 12 dB range and
implemented within the ADC by adjusting its full-scale reference
level. Increasing the ADC’s full scale is equivalent to attenuating
the signal. An additional 12 dB of digital gain range is achieved
by scaling the output of the decimation filter in the DVGA. Note,
a slight increase in the supply current (i.e., 0.67 mA) is drawn from
VDDI and VDDF as the VGA changes from 0 dB to 12 dB attenuation.
The purpose of the VGA is to extend the usable dynamic range
of the AD9874 by allowing the ADC to digitize a desired signal
over a large input power range as well as recover a low level signal
in the presence of larger unfiltered interferers without saturating
or “clipping” the ADC. The DVGA is most useful in extending
the dynamic range in narrow-band applications requiring a 16-bit
I and Q data format. In these applications, quantization noise
resulting from internal truncation to 16 bits as well as external
16-bit fixed point post-processing can degrade the AD9874’s
effective noise figure by 1 or more dB. The DVGA is enabled by
writing a 1 to the AGCV field. The VGA (and the DVGA) can
operate in either a user-controlled Variable Gain Mode or Auto-
matic Gain Control (AGC) Mode.
It is worth noting that the VGA imparts negligible phase error
upon the desired signal as its gain is varied over a 12 dB range.
This is due to the bandwidth of the VGA being far greater than
the down converted desired signal (centered about f
remaining relatively independent of gain setting. As a result, phase
modulated signals should experience minimal phase error as the
AGC varies the VGA gain while tracking an interferer or the desired
signal under fading conditions. Note, the envelope of the signal
will still be affected by the AGC settings.
REV. 0
GCP
- ADC
FS
C
DAC
DEC1
VGA
DAC
12
Figure 18. Functional Block Diagram of VGA and AGC
DEC2
DEC3
AND
I + Q
I + Q
CLK
/8) and
LARGER
SELECT
–27–
REF LEVEL
AGCR
+
AGCA/AGCD
Variable Gain Control
The variable gain control is enabled by setting the AGCR field
of Register 0x06 to 0. In this mode, the gain of the VGA (and the
DVGA) can be adjusted by writing to the 16-bit AGCG Register.
The maximum update rate of the AGCG Register via the SPI port
is f
of attenuation in the mixer. This feature allows the AD9874 to
cope with large level signals beyond the VGA’s range (i.e.,
> –18 dBm at LNA input) to prevent overloading of the ADC.
The lower 15 bits specify the attenuation in the remainder of the
signal path. If the DVGA is enabled, the attenuation range is from
–12 dB to +12 dB since the DVGA provides 12 dB of digital gain.
In this case, all 15 bits are significant. However, with the DVGA
disabled the attenuation range extends from 0 dB to 12 dB and
only the lower 14 bits are useful. Figure 19 shows the relationship
between the amount of attenuation and the AGC Register setting
for both cases.
SCALING
Figure 19. AGC Gain Range Characteristics vs. AGCG
Register Setting with and without DVGA Enabled
CLK
K
–12
/240. The MSB of this register is the bit that enables 16 dB
12
–6
0000
6
0
(1 – Z
VGA ENABLED
1
RSSI DATA
–1
ONLY
)
SETTING
AGCV
VGA ENABLED
1FFF
DVGA AND
AGCG SETTING – HEX
3FFF
DVGA
I/Q DATA
TO SSI
TO SSI
5FFF
AD9874
7FFF
RANGE
RANGE
DVGA
VGA