AD9874BST AD [Analog Devices], AD9874BST Datasheet - Page 9

• Manufacturer Part Number: AD9874BST
• Description: IF Digitizing Subsystem
• Manufacturer: AD [Analog Devices]

(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f
T
TPC 7a. Normalized Gain Variation
vs. LO Drive (VDDx = 3.0 V)
TPC 8a. Complex FFT of Baseband
I/Q for Single-Tone (High Bias)
TPC 9a. Complex FFT of Baseband
I/Q for Dual Tone IMD (High Bias
with each IFIN Tone @ –35 dBm)
1
2
3
REV. 0
Data taken with Toko FSLM series 10 µH inductors
High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01
Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01
A
–100
–120
–140
–100
–120
–140
= 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–20
–40
–60
–80
–20
–40
–60
–80
0.1
–80 –60 –40 –20
0
–80 –60 –40 –20
0
0
–20
–18.2dBFS OUTPUT
–2.8 dBFS OUTPUT
LOW BIAS
IMD = 74dBc
–17
FREQUENCY – kHz
FREQUENCY – kHz
HIGH BIAS
LO DRIVE – dBm
–14
0
0
–11
20
20
MAX VGA ATTEN
NBW = 3.66kHz
f
DEC–BY–120
MAX VGA ATTEN
CLK
NBW = 3.66kHz
f
DEC–BY–120
CLK
40
40
= 18MHz
–8
= 18MHz
60
60
–5
80
80
TPC 8b. Gain Compression vs. IFIN
(High Bias
TPC 9b. IMD vs. IFIN (High Bias
–100
–106
–112
–118
–124
–130
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
–70
–76
–82
–88
–94
–10
–12
–14
–20
TPC 7b. Noise Figure and IMD
vs. LO Drive (VDDx = 3.0 V)
–2
–4
–6
–8
–30
–51
0
–28
–48
–15
2
)
2.7V
–26
–45
LO DRIVE – dBm
–10
“HARD COMPRESSION”
3.3V
IFIN – dBm
IFIN – dBm
–24
PIN
–42
–9–
IMD-HIGH BIAS
IMD-LOW BIAS
NF-HIGH BIAS
ADC GOES INTO
NF-LOW BIAS
3.6V
–22
2.7V
–39
–5
3.0V
3.6V
–20
–36
3.3V
0
CLK
–18
3.0V
–33
= 18 MSPS, f
2
)
5
–16
–30
–10
–20
–30
–40
–50
–60
–70
–80
0
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
IF
TPC 7c. Gain Compression vs. IFIN
with 16 dB LNA Attenuator Enabled
TPC 8c. Gain Compression vs. IFIN
(Low Bias
TPC 9c. IMD vs. IFIN (Low Bias
= 109.56 MHz, f
–103
–109
–115
–67
–97
–55
–61
–73
–79
–85
–91
–12
–15
–18
–21
–24
–27
–30
–33
–36
–10
–12
–14
–2
–4
–6
–8
–51
0
–30
–36
–33 –30 –27 –24 –21 –18 –15 –12 –9 –6 –3
–48
–28 –26 –24 –22 –20 –18
3
)
2.7V
–45
LO
ADC DOES NOT GO INTO
“HARD COMPRESSION”
= 107.4 MHz,
IFIN – dBm
3.3V
1
PIN
–42
IFIN – dBm
IFIN – dBm
HIGH BIAS
3.6V
2.7V
–39
AD9874
3.6V
3.0V
LOW BIAS
–36
3.3V
3.0V
–33
–16
3
)
–30
–14
0
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45