STLC5412FN STMICROELECTRONICS [STMicroelectronics], STLC5412FN Datasheet - Page 21

• Manufacturer Part Number: STLC5412FN
• Description: 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Data is transmitted in both directions at half the
data clock rate. The information is clocked by the
transmitter on the front edge of the data clock and
can be accepted by the receiver after 1 to 1.5 pe-
riod of the data clock.
The data clock (BCLK) is a square wave signal at
twice the data transmission frequency on Bx and
Br with a 1 to 1 duty cycle. The frequency can be
choosen from 512
modularity. Data transmission rate depends only
on the data clock rate.
Table 1: GCI Configuration selection.
(1) Differentation between LT and NT configuration done by bit NTS in CR2 register; GCI in slave mode.
When NT1-AUTO or NT-RR-AUTO configuration is selected, BCLK bit clock frequency of 512 kHz is
automatically selected
When NT configuration is selected, BCLK bit clock frequency of 1536 kHz is automatically selected.
(2) Connected to V
PLCC44
43
42
27
25
10
26
24
23
22
35
Pin Number
DIP28
28
27
19
17
18
16
15
14
22
7
CC
S0/FSb/TEST2
IO4/TEST1 (2)
SFSx/RFS (2)
IO1/ES1 (2)
IO2/ES2 (2)
S1/CONF1
S2/CONF2
IO3/EC (2)
through internal pull-up resistors.
to 6176 kHz with 16 kHz
Pin name
MW
M0
LT/NT12 (1)
SFSx
IO1
IO2
IO3
IO4
S1
S2
S0
0
0
NT/TE
SFSx
FSb
IO1
IO2
IO3
IO4
0
1
0
1
The Frame Clock FSa is a 8 kHz signal for syn-
chronization of data transmission. The front edge
of this signal gives the time reference of the first
bit in the first GCI input and output channel, and
reset the slot counter at the start of each frame.
When some GCI channels are not selected on
devices connected to the same GCI link, these
time slots are free for alternative uses.
GCI configuration selection is done by biasing of
input pins MW, M0, CONF1, CONF2 according to
Table 1.
Configuration
NT1-AUTO
TEST2
TEST1
SFSx
ES1
ES2
EC
0
1
1
1
LT-RR-AUTO NT-RR-AUTO
TEST2
TEST1
PLDD
RFS
LFS
EC
0
1
1
0
STLC5412
TEST2
TEST1
RFS
ES1
ES2
LFS
0
1
0
0
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