STLC5412FN STMICROELECTRONICS [STMicroelectronics], STLC5412FN Datasheet - Page 42

• Manufacturer Part Number: STLC5412FN
• Description: 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STLC5412
Overhead bits Programmable Register (OPR)
After reset: 1EH
CIE Near-End CRC Interrupt Enable:
42/74
area 00/0FH: NOP operations.
area 10/1FH: test registers: reserved.
area 20/2FH: the configuration registers.
area 30/3FH: the B1 B2 D time slot registers.
area 40/4FH: the transmit and receive
area 5x to Bx:
area C0/C3H:
areaC4HtoEx:
area Fx:
CIE
5x:
6x:
7x:
8x & 9x:
Ax:
Bx:
EIE
FIE
OPR CR1 CR2 CR3 CR4 CR5
CR6 CR7
Read Write access. CR5 only
usefull in GCI mode
TXB1 TXB2 RXB1 RXB2 TXD
RXD STATUS
Read Write access except
STATUS: Read only.
Usefull only in W mode
except STATUS: W & GCI
modes.
registers (except EOC).
TXM4 RXM4 TXM56 RXM56
TXACT RXACT BEC1 BEC2
ECT1 ECT2 RXOH
Read Write access for the
transmit registers:
Read access only for the
receive registers:
Read Write access for the
control registers:
Read access only for the error
registers:
Write access only for the
command registers:
for 12 bits registers.
to write TXEOC register, to read
RXEOC register.
to read TXEOC register.
reserved
to read IDR register.
to write DECTEOC register
to read DECTEOC register
to read round trip delay registers
reserved
reserved except FF address:
special register MWPS.
TXM4 TXM56 TXACT
RXM4 RXM56 RXACT
ECT1 ECT2
BEC1 BEC2
RXOH
OB1
OB0
OC1
OC0
C2E
EIE Error counting Interrupt Enable:
FIE FEBE lnterrupt Enable:
OB1, OB0 Overhead Bit processing:
select how each spare overhead bit received from
the line is validated and transmitted to the sys-
tem. RXM4 and RXM56 registers are inde-
pendently provided onto the system interface as
for the eoc channel. Each spare overhead bit is
validated independentlyfrom the others.
If new bits are received at the same time in M4
CIE = 1: the RXM56 register is queued in the
CIE = 0: no interrupt is issued but the error
EIE = 1: an interrupt is provided for the
EIE= 0:
FIE = 1:
FIE = 0:
OB1
0
0
1
1
OB0
counter when the threshold (ECT1 or
ECT2) is reached.
no interrupt is issued. It is feasible to
read the counters even if no relevant
interrupt has been provided.
interrupt register stack with nebe bit
set to zero each time the CRC result
is not identical to the corresponding
CRC received from the line.
detection remains active for instance
for on chip error counting.
the RXM56 register is queued into
the interrupt register stack each time
the febe bit is received at zero in a
superframe.
no interrupt is issued but the receive
febe bit remains active for on chip
error counting.
0
1
0
1
each super frame, an interrupt
is generated for the RXM4 or
the RXM56 register. Spare bits
are transparently transmited to
the system.
an interrupt is set at each new
spare overhead bit(s) received.
an interrupt is set at each new
spare overhead bit(s) received
and confirmed once. ( two
times identical).
an interrupt is set at each new
spare overhead bit(s) received
and confirmed twice. (three
times identical).