STLC5412FN STMICROELECTRONICS [STMicroelectronics], STLC5412FN Datasheet - Page 24

• Manufacturer Part Number: STLC5412FN
• Description: 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

STLC5412
vided on SFSx output by the rising edge of a 12
ms period square wave signal. LT or NT, when
pin 25 is selected as SFSr by mean of bit ESFr in
CR4, SFSr is a square wave open drain output in-
dicating the received superframe on the line. (see
figure 7). Prior to transmisssion, all data, with the
exception of the sync-word,is scrambled using a
self-synchronizing scrambler to perform the speci-
fied 23rd-order polynomial. Descrambling is in-
cluded in the receiver. Polynomial is different de-
pending on the direction LT to NT or vice versa.
TRANSMIT SECTION
Data transmitted to the line consists of the 2B+D
channel data received from the Digital Interface
through an elastic data buffer allowing any phase
deviation with the line, the activation/deactivation
bits (M4) from the on-chip activation sequencer,
the CRC code plus maintenance data (eoc chan-
nels) and other spare bits in the overhead chan-
nels (M4, M5, M6). Data is multiplexed and
scrambled prior to addition of the sync-word,
which is generated within the device. A pulse
waveform synthesizer then drives the transmit fil-
ter, which in turn passes the line signal to the line
driver. The differential line-driver outputs, LO+,
LO- are designed to drive a transformer through
an external termination circuit. A 1:1.5 trans-
former designed as shown in the STLC5412 user
guide, results in a signal amplitude of 2.5V pk
nominal on the line for single quats of the +3
level. (see output pulse template fig.8). Short-cir-
cuit protection is included in the output stage;
over-voltage protection must be provided exter-
nally.
In LT applications, the Network reference clock
given by the FSa 8kHz clock input synchronizes
the transmitted data to the line. The Digital Inter-
face normally accepts BCLK and FSa signals
from the network, requiring the selection of Slave
Mode in CR1. A Digital Phase-Locked Loop
(DPLL 1) on the UID allows the SCLK frequency
to be plesiochronous with respect to the network
reference clock (8 kHz FSa input). With a toler-
ance on the XTAL1 oscillator of 15.36 MHz +/-
100 ppm, the lock-in range of DPLL1 allows the
network clock frequency to deviate up to +/-
50ppm from nominal.
In LT, if DSI is selected in Master mode, (Mi-
crowire only, bit CMS = 1 in CR1), BCLK and FSa
signals are outputs frequency synchronized to
XTAL1 input, DPLL 1 is disabled.
In NT applications, data is transmitted to the line
with a phase deviation of half a frame relative to
the received data as specified in the ANSI stand-
ard.
RECEIVE SECTION
The receive input signal should be derived from
the transformer by a coupling circuit as shown in
24/74
the user guide. At the front end of the receive
section is a continuous filter which limits the noise
bandwidth to approximately 100kHz. Then, an
analog pre-canceller provides a degree of echo
cancellation in order to limit the dynamic range of
the composite signal which noise bandwidth lim-
ited by a 4th order Butterworth switched capacitor
low pass filter. After an automatic gain control, a
13bits A/D converter then samples the composite
received signal before the echo cancellation from
local transmitter by means of an adaptive digital
transversal filter. The attenuation and distortion of
the received signal from the far-end, caused by
the line, is equalized by a second adaptive digital
filter configured as a Decision Feedback Equal-
izer (DFE), that restores a flat channel response
with maximum received eye opening over a wide
spread of cable attenuation characteristics.
A timing recovery circuit based on a DPLL (Digital
Phase-Locked Loop) recovers a very low-jitter
clock for optimum sampling of the received sym-
bols. The 15.36MHz crystal oscillator (or the logic
level clock input) provides the reference clock for
the DPLL. In NT configuration, SCLK output pro-
vides a very low jitter 15.36MHz clock synchro-
nized from the line.
Received data is then detected and flywheel syn-
chronization circuit searches for and locks onto
the frame and superframe syncwords. STLC5412
is frame-synchronized when two consecutive
synchwords have been consecutively detected.
Frame lock will be maintained until six consecu-
tive errored sync-words are detected, which will
cause the flywheel to attempt to re-synchronize. If
a loss of frame sync condition persists for 480ms
the device will cease searching, cease transmit-
ting and go automatically into the RESET state,
ready for a further cold start. When UID is frame-
synchronized, it is superframe-locked upon the
first superframe sync-word detection. No loss of
superframe sync-word is provided.
While the receiver is synchronized, data is de-
scrambled using the specified polynomial, and in-
dividual channels demultiplexed and passed to
their respective processing circuits: user’s 2B+D
channel data is transmitted to the Digital Interface
through an elastic data buffer allowing any phase
deviation with the line; the activation/deactivation
bits (M4) are transmitted to the on-chip activation
sequencer; CRC is transmitted to CRC checking
section while maintenance data (eoc) and other
spare bits in the overhead channels (M4, M5, M6)
are stored in their respective Rx registers.
In NT applications, if the Digital Interface is se-
lected in master mode (see CR1) BCLK and FSa
clock outputs are phase-locked to the recovered
clock. If it is selected in Slave mode ie for NT1-2
application, the on-chip elastic buffers allow
BCLK and FSa to be input from an external
source, which must be frequency locked to the re-
ceived line signal ie using the SCLK output but