STLC5412FN STMICROELECTRONICS [STMicroelectronics], STLC5412FN Datasheet - Page 43

• Manufacturer Part Number: STLC5412FN
• Description: 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

and M56, both registers RXM4 and RXM56 are
queued in the interrupt register stack.
Bits act, dea, uoa, sai are dedicated to the activa-
tion procedure. Validation is always done in ac-
cordance with the ANSI rule: validation at each
new activation bit received and confirmed twice
independently from the above rules. These bits
are taken into account directly by the activation
decoder. An interrupt is not generated for the
RXM4 Register when one of these bits changes,
but they are provided for test to the RXM4 Regis-
ter.
OC1, OC0 eoc channel processing:
select how a received eoc message is validated
and transmitted to the system.
C2E Counter 2 enable:
C2E = 0: Only counter BEC1 is used for both febe
C2E = 1: Counter BEC1 is used for nebe.
Configuration Register 1 (CR1)
After reset:
GCI: MO = 0 (LT/NT12) = C0H
GCI: MO = 1 (NT/TE) = D2H
FF1, FF0 Frame Format Selection: ( W/DSI only)
Refer to fig. 2 and 3.
W mode 00H
FF1
OC1
FF1
0
0
1
1
0
0
1
1
FF0
and nebe counting.
Counter BEC2 is used for febe.
OC0
FF2
0
1
0
1
0
1
0
1
CK2
every half a super frame, an
interrupt is generated for the
RXEOC register. eoc channel
is transparently transmitted to
the system.
an interrupt is set at each new
eoc message received.
an interrupt is set at each new
eoc message received and
confirmed once. (two times
identical)
an interrupt is set at each new
eoc message received and
confirmed twice. (three times
identical).
Format 1
Format 2
Format 3
Format 4 GCI like
CK1
CK0 DDM CMS BEX
CK0-CK2 Digital Interface Clock select: ( W/DSI
only)
CK0-CK2 bits select the BCLK output frequency
when DSI clocks are outputs.
DDM Delayed Data Mode select:( W/DSI only)
Two different phase-relations may be established
between the Frame Sync signals and the first bit
of the frame on the Digital Interface:
CMS Clocks Master Select:( W/DSI only)
BEX B channels EXchange:
Configuration Register 2 (CR2)
After reset:
GCI: MO = 0 (LT/NT12) = 00H
GCI: MO = 1 (NT/TE) = 80H
GCI (LT,NT):
SFS Super Frame Synchronization Select:
Significant in LT mode only.
DDM = 0: Non delayed data mode The first bit
DDM = 1: delayed data mode: FSA/B input must
CMS = 0: BCLK, FSA and FSB are inputs;
CMS = 1: BCLK, FSA and FSB are outputs. FSA
BEX = 0: B1 and B2 Tx/Rx channels are
BEX = 1: B1 and B2 channels are exchanged.
SFS NTS DMO DEN ETC BP1
SFS NTS T24D CID ETC BP1
W mode 00H
W (LT,NT):
CK2
0
0
0
0
1
CK1
of
coincident with the rising edge of
FSA/B.
be set high at least a half cycle of
BCLK earlier the frame beginning.
associated
TXB2/RXB2 registers respectively.
0
0
1
1
0
BCLK can have in Format 1, 2 and 3
value between 256KHz to 4096KHz,
value in
6176KHz.
is a 8 kHz clock pulse indicating the
frame beginning. FSB is a 8 kHz clock
pulse indicating the second 8 bits wide
time-slot. BCLK is a bit clock signal
whose frequency is fixed bits CK2-CK0.
the
CK0
0
1
0
1
0
frame
Format
with
BCLK frequency:
EIF
EIF
begins
TXB1/RXB1
1536KHz
2048KHz
2560KHz
256KHz
512KHz
4:
BFH9D
BFH9D
BP2
BP2
512KHz to
STLC5412
nominally
43/74
RR
RR
and